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Remove the 'when' parameter from 'add_cons' (Vivado-specific)
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@rodrigomelo9
rodrigomelo9 committed Aug 11, 2024
1 parent 9085338 commit e1c6ebf
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Showing 11 changed files with 45 additions and 52 deletions.
12 changes: 6 additions & 6 deletions docs/internals.rst
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Expand Up @@ -39,15 +39,15 @@ Internal data structure
'part': 'PARTNAME',
'includes': ['DIR1', 'DIR2', 'DIR3'],
'files': {
'FILE1': {'hdl': 'vhdl', 'lib': 'LIB1'}
'FILE2': {'hdl': 'vlog'},
'FILE3': {'hdl': 'slog'}
'FILE1': {'hdl': 'vhdl', 'lib': 'LIB1', 'opt': 'OPTS'},
'FILE2': {'hdl': 'vlog', 'opt': 'OPTS'},
'FILE3': {'hdl': 'slog', 'opt': 'OPTS'}
},
'top': 'TOPNAME',
'constraints': {
'FILE1': 'all',
'FILE2': 'syn',
'FILE3': 'par'
'FILE1': {'opt': 'OPTS'},
'FILE2': {'opt': 'OPTS'},
'FILE3': {'opt': 'OPTS'}
},
'params': {
'PAR1': 'VAL1',
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5 changes: 3 additions & 2 deletions examples/hooks/vivado.py
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Expand Up @@ -33,9 +33,10 @@
set_property "steps.opt_design.args.directive" "ExploreArea" $obj
''')

place = ['../sources/cons/ZYBO/clk.xdc', '../sources/cons/ZYBO/led.xdc']
prj.add_hook('postcfg', f'''
set_property USED_IN_SYNTHESIS FALSE [get_files {Path('../sources/cons/ZYBO/clk.xdc').resolve()}]
set_property USED_IN_SYNTHESIS FALSE [get_files {Path('../sources/cons/ZYBO/led.xdc').resolve()}]
set_property USED_IN_SYNTHESIS FALSE [get_files {Path(place[0]).resolve()}]
set_property USED_IN_SYNTHESIS FALSE [get_files {Path(place[1]).resolve()}]
''')

prj.make()
12 changes: 6 additions & 6 deletions examples/projects/ise.py
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Expand Up @@ -22,15 +22,15 @@
if args.board == 's6micro':
prj.set_part('xc6slx9-2-csg324')
prj.add_param('FREQ', '125000000')
prj.add_cons('../sources/cons/s6micro/clk.xcf', 'syn')
prj.add_cons('../sources/cons/s6micro/clk.ucf', 'par')
prj.add_cons('../sources/cons/s6micro/led.ucf', 'par')
prj.add_cons('../sources/cons/s6micro/clk.xcf')
prj.add_cons('../sources/cons/s6micro/clk.ucf')
prj.add_cons('../sources/cons/s6micro/led.ucf')
if args.board == 'nexys3':
prj.set_part('xc6slx16-3-csg32')
prj.add_param('FREQ', '100000000')
prj.add_cons('../sources/cons/nexys3/clk.xcf', 'syn')
prj.add_cons('../sources/cons/nexys3/clk.ucf', 'par')
prj.add_cons('../sources/cons/nexys3/led.ucf', 'par')
prj.add_cons('../sources/cons/nexys3/clk.xcf')
prj.add_cons('../sources/cons/nexys3/clk.ucf')
prj.add_cons('../sources/cons/nexys3/led.ucf')
prj.add_param('SECS', '1')

if args.source == 'vhdl':
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6 changes: 3 additions & 3 deletions examples/projects/libero.py
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Expand Up @@ -21,9 +21,9 @@
if args.board == 'maker':
prj.set_part('m2s010-1-tq144')
prj.add_param('FREQ', '125000000')
prj.add_cons('../sources/cons/maker/clk.sdc', 'syn')
prj.add_cons('../sources/cons/maker/clk.pdc', 'par')
prj.add_cons('../sources/cons/maker/led.pdc', 'par')
prj.add_cons('../sources/cons/maker/clk.sdc')
prj.add_cons('../sources/cons/maker/clk.pdc')
prj.add_cons('../sources/cons/maker/led.pdc')
prj.add_param('SECS', '1')

if args.source == 'vhdl':
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16 changes: 8 additions & 8 deletions examples/projects/openflow.py
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Expand Up @@ -23,23 +23,23 @@
if args.board == 'icestick':
prj.set_part('hx1k-tq144')
prj.add_param('FREQ', '100000000')
prj.add_cons('../sources/cons/icestick/clk.pcf', 'par')
prj.add_cons('../sources/cons/icestick/led.pcf', 'par')
prj.add_cons('../sources/cons/icestick/clk.pcf')
prj.add_cons('../sources/cons/icestick/led.pcf')
if args.board == 'edu-ciaa':
prj.set_part('hx1k-tq144')
prj.add_param('FREQ', '100000000')
prj.add_cons('../sources/cons/edu-ciaa/clk.pcf', 'par')
prj.add_cons('../sources/cons/edu-ciaa/led.pcf', 'par')
prj.add_cons('../sources/cons/edu-ciaa/clk.pcf')
prj.add_cons('../sources/cons/edu-ciaa/led.pcf')
if args.board == 'orangecrab':
prj.set_part('25k-CSFBGA285')
prj.add_param('FREQ', '100000000')
prj.add_cons('../sources/cons/orangecrab/clk.lpf', 'par')
prj.add_cons('../sources/cons/orangecrab/led.lpf', 'par')
prj.add_cons('../sources/cons/orangecrab/clk.lpf')
prj.add_cons('../sources/cons/orangecrab/led.lpf')
if args.board == 'ecp5evn':
prj.set_part('um5g-85k-CABGA381')
prj.add_param('FREQ', '100000000')
prj.add_cons('../sources/cons/ecp5evn/clk.lpf', 'par')
prj.add_cons('../sources/cons/ecp5evn/led.lpf', 'par')
prj.add_cons('../sources/cons/ecp5evn/clk.lpf')
prj.add_cons('../sources/cons/ecp5evn/led.lpf')
prj.add_param('SECS', '1')

if args.source == 'vhdl':
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6 changes: 3 additions & 3 deletions examples/projects/quartus.py
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Expand Up @@ -22,9 +22,9 @@
if args.board == 'de10nano':
prj.set_part('5CSEBA6U23I7')
prj.add_param('FREQ', '125000000')
prj.add_cons('../sources/cons/de10nano/clk.sdc', 'syn')
prj.add_cons('../sources/cons/de10nano/clk.tcl', 'par')
prj.add_cons('../sources/cons/de10nano/led.tcl', 'par')
prj.add_cons('../sources/cons/de10nano/clk.sdc')
prj.add_cons('../sources/cons/de10nano/clk.tcl')
prj.add_cons('../sources/cons/de10nano/led.tcl')
prj.add_param('SECS', '1')

if args.source == 'vhdl':
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12 changes: 6 additions & 6 deletions examples/projects/vivado.py
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Expand Up @@ -22,15 +22,15 @@
if args.board == 'zybo':
prj.set_part('xc7z010-1-clg400')
prj.add_param('FREQ', '125000000')
prj.add_cons('../sources/cons/ZYBO/timing.xdc', 'syn')
prj.add_cons('../sources/cons/ZYBO/clk.xdc', 'par')
prj.add_cons('../sources/cons/ZYBO/led.xdc', 'par')
prj.add_cons('../sources/cons/ZYBO/timing.xdc')
prj.add_cons('../sources/cons/ZYBO/clk.xdc')
prj.add_cons('../sources/cons/ZYBO/led.xdc')
if args.board == 'arty':
prj.set_part('xc7a35ticsg324-1L')
prj.add_param('FREQ', '100000000')
prj.add_cons('../sources/cons/arty_a7_35t/timing.xdc', 'syn')
prj.add_cons('../sources/cons/arty_a7_35t/clk.xdc', 'par')
prj.add_cons('../sources/cons/arty_a7_35t/led.xdc', 'par')
prj.add_cons('../sources/cons/arty_a7_35t/timing.xdc')
prj.add_cons('../sources/cons/arty_a7_35t/clk.xdc')
prj.add_cons('../sources/cons/arty_a7_35t/led.xdc')
prj.add_param('SECS', '1')

if args.source == 'vhdl':
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9 changes: 3 additions & 6 deletions pyfpga/project.py
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Expand Up @@ -123,22 +123,19 @@ def add_vlog(self, pathname):
self.logger.debug('Executing add_vlog')
self._add_file(pathname, 'vlog')

def add_cons(self, path, when='all'):
def add_cons(self, path):
"""Add a constraint file.
:param pathname: path of a file
:type pathname: str
:param when: always ('all'), synthesis ('syn') or P&R ('par')
:type only: str, optional
:raises FileNotFoundError: if path is not found
"""
self.logger.debug('Executing add_cons')
path = Path(path).resolve()
if not path.is_file():
raise FileNotFoundError(path)
if when not in ['all', 'syn', 'par']:
raise ValueError('Invalid only.')
self.data.setdefault('constraints', {})[path.as_posix()] = when
attr = {}
self.data.setdefault('constraints', {})[path.as_posix()] = attr

def add_param(self, name, value):
"""Add a Parameter/Generic Value.
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5 changes: 0 additions & 5 deletions pyfpga/templates/vivado.jinja
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Expand Up @@ -25,11 +25,6 @@ add_file {{ name }}
{% if constraints %}# Constraints inclusion
{% for name, attr in constraints.items() %}
add_file -fileset constrs_1 {{ name }}
{% if attr == "syn" %}
set_property USED_IN_IMPLEMENTATION FALSE [get_files {{ name }}]
{% elif attr == "par" %}
set_property USED_IN_SYNTHESIS FALSE [get_files {{ name }}]
{% endif %}
{% if loop.first %}set_property TARGET_CONSTRS_FILE {{ name }} [current_fileset -constrset]{% endif %}
{% endfor %}
{% endif %}
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10 changes: 5 additions & 5 deletions tests/test_data.py
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Expand Up @@ -52,9 +52,9 @@
},
'top': 'TOPNAME',
'constraints': {
Path(tdir / 'fakedata/cons/all.xdc').resolve().as_posix(): 'all',
Path(tdir / 'fakedata/cons/syn.xdc').resolve().as_posix(): 'syn',
Path(tdir / 'fakedata/cons/par.xdc').resolve().as_posix(): 'par'
Path(tdir / 'fakedata/cons/all.xdc').resolve().as_posix(): {},
Path(tdir / 'fakedata/cons/syn.xdc').resolve().as_posix(): {},
Path(tdir / 'fakedata/cons/par.xdc').resolve().as_posix(): {}
},
'params': {
'PAR1': 'VAL1',
Expand Down Expand Up @@ -90,8 +90,8 @@ def test_data():
prj.add_vhdl(str(tdir / 'fakedata/**/*.vhdl'), 'LIB')
prj.add_vlog(str(tdir / 'fakedata/**/*.v'))
prj.add_cons(str(tdir / 'fakedata/cons/all.xdc'))
prj.add_cons(str(tdir / 'fakedata/cons/syn.xdc'), 'syn')
prj.add_cons(str(tdir / 'fakedata/cons/par.xdc'), 'par')
prj.add_cons(str(tdir / 'fakedata/cons/syn.xdc'))
prj.add_cons(str(tdir / 'fakedata/cons/par.xdc'))
prj.add_param('PAR1', 'VAL1')
prj.add_param('PAR2', 'VAL2')
prj.add_param('PAR3', 'VAL3')
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4 changes: 2 additions & 2 deletions tests/test_tools.py
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Expand Up @@ -54,8 +54,8 @@ def generate(tool, part):
prj.add_vhdl(str(tdir / 'fakedata/**/*.vhdl'), 'LIB')
prj.add_vlog(str(tdir / 'fakedata/**/*.v'))
prj.add_cons(str(tdir / 'fakedata/cons/all.xdc'))
prj.add_cons(str(tdir / 'fakedata/cons/syn.xdc'), 'syn')
prj.add_cons(str(tdir / 'fakedata/cons/par.xdc'), 'par')
prj.add_cons(str(tdir / 'fakedata/cons/syn.xdc'))
prj.add_cons(str(tdir / 'fakedata/cons/par.xdc'))
prj.add_param('PAR1', 'VAL1')
prj.add_param('PAR2', 'VAL2')
prj.add_define('DEF1', 'VAL1')
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