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fix: ommission in refactor
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mstechly committed Jun 19, 2024
1 parent c5db30d commit 8dfe5cb
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions src/bartiq/compilation/_evaluate.py
Original file line number Diff line number Diff line change
Expand Up @@ -177,8 +177,8 @@ def _evaluate_over_assignment(
subroutine_assignments.append(assignment)

# Check for any register size assignments that have been propagated from upstream ports
if subroutine.absolute_path in register_sizes:
subroutine_assignments.extend(register_sizes.pop(subroutine.absolute_path))
if subroutine.absolute_path() in register_sizes:
subroutine_assignments.extend(register_sizes.pop(subroutine.absolute_path()))

# Compute the new routine
evaluated_routine = _evaluate_routine(subroutine, subroutine_assignments, backend, functions_map)
Expand Down Expand Up @@ -206,7 +206,7 @@ def _get_downstream_register_size_assignments(source_port: Port, value: Number)
variable = str(target_port.size)
local_assignment = _RegisterSizeAssignment(target_port.direction, target_port.name, variable, value)
assert target_port.parent is not None
register_sizes[target_port.parent.absolute_path].append(local_assignment)
register_sizes[target_port.parent.absolute_path()].append(local_assignment)

return register_sizes

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