Merge pull request #147 from zhanghongce/master

VTG: parameter parser update & re-structure
PrincetonUniversity · Sep 6, 2019 · ff6c1a0 · ff6c1a0
2 parents ebe080b + 5212204
commit ff6c1a0
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Showing 11 changed files with 858 additions and 667 deletions.
diff --git a/include/ilang/util/str_util.h b/include/ilang/util/str_util.h
@@ -24,6 +24,9 @@ bool StrToBool(const std::string& str);
 /// Return the value represented in the string, e.g. "10".
 int StrToInt(const std::string& str, int base = 10);
 
+/// Return the value represented in the string in long type, e.g. "10".
+long long StrToLong(const std::string& str, int base);
+
 /// Python-style split , return a vector of splitted strings
 std::vector<std::string> Split(const std::string& str,
                                const std::string& delim);

diff --git a/src/util/str_util.cc b/src/util/str_util.cc
@@ -39,6 +39,15 @@ int StrToInt(const std::string& str, int base) {
 }
 
 
+long long StrToLong(const std::string& str, int base) {
+  try {
+    return std::stoll(str, NULL, base);
+  } catch (const std::exception& e) {
+    ILA_ERROR << "Converting non-numeric value " << str << " to long int.\n";
+    return 0;
+  }
+}
+
 std::vector<std::string> Split(const std::string& str,
                                const std::string& delim) {
   std::vector<std::string> tokens;

diff --git a/src/verilog-in/verilog_analysis.cc b/src/verilog-in/verilog_analysis.cc
@@ -692,8 +692,8 @@ VerilogAnalyzer::module_io_vec_t VerilogAnalyzer::get_top_module_io() const {
       void* ptr_from_list_ =
           ast_list_get_not_null(port_ptr->port_names, name_idx);
       ast_identifier port_id_ptr;
-      if (port_ptr
-              ->is_reg) { // in this case, it is not a list of ast_identifier
+      if (! port_ptr
+              ->is_list_id) { // in this case, it is not a list of ast_identifier
         // but a list of ast_single_assignment(ast_new_lvalue_id)
         ast_single_assignment* asm_ptr = (ast_single_assignment*)ptr_from_list_;
         ILA_ASSERT(asm_ptr->lval->type == ast_lvalue_type_e::NET_IDENTIFIER ||

diff --git a/src/verilog-in/verilog_const_parser.cc b/src/verilog-in/verilog_const_parser.cc
@@ -14,6 +14,12 @@ VerilogConstantExprEval::VerilogConstantExprEval() : eval_error(false) {
   // do nothing
 }
 
+static void* ast_list_get_not_null(ast_list* list, unsigned int item) {
+  void* ret = ast_list_get(list, item);
+  ILA_NOT_NULL(ret);
+  return ret;
+}
+
 double
 VerilogConstantExprEval::_eval(ast_expression* e,
                                const named_parameter_dict_t& param_defs) {
@@ -51,7 +57,7 @@ VerilogConstantExprEval::_eval(ast_expression* e,
                                       ast_number_base_e::BASE_HEX
                                   ? 16
                                   : 10;
-        ret = StrToInt(resp, base);
+        ret = StrToLong(resp, base);
       } else { // float
         try {
           ret = std::stod(resp);
@@ -72,6 +78,30 @@ VerilogConstantExprEval::_eval(ast_expression* e,
           return 0;
         }
       return _eval(e->primary->value.minmax->aux, param_defs);
+    } else if (e->primary->value_type == ast_primary_value_type::PRIMARY_CONCATENATION) {
+      ast_concatenation * cc = e->primary->value.concatenation;
+      unsigned repeat = cc->repeat? _eval(cc->repeat, param_defs ) : 1;
+      unsigned total_width = 0;
+      long long ret = 0;
+      for (size_t idx = 0; idx < cc->items->items; ++idx) {
+        ast_expression * it = (ast_expression *)ast_list_get_not_null(cc->items, idx);
+        unsigned v = _eval(it, param_defs);
+        unsigned width = it->primary->value.number->width;
+        if (width == 0) {
+          error_str = ast_expression_tostring(e);
+          eval_error = true;
+          return 0;
+        }  
+        ret = ret << width;
+        ret = ret | v;        
+        total_width += width;
+      }
+      unsigned origin = ret;
+      for (unsigned idx = 1; idx < repeat; ++ idx) {
+        ret = ret << total_width;
+        ret = ret | origin;
+      }
+      return ret;
     }
      else { // parser error: unable to handle
       error_str = ast_expression_tostring(e);
@@ -95,10 +125,23 @@ VerilogConstantExprEval::_eval(ast_expression* e,
       return left / right;
     if (e->operation == ast_operator::OPERATOR_MOD)
       return left % right;
+    if (e->operation == ast_operator::OPERATOR_L_OR)
+      return left || right;
+    if (e->operation == ast_operator::OPERATOR_L_AND)
+      return left && right;
+    if (e->operation == ast_operator::OPERATOR_B_OR)
+      return left | right;
+    if (e->operation == ast_operator::OPERATOR_B_AND)
+      return left & right;
 
     eval_error = true;
     error_str = ast_expression_tostring(e);
     return 0;
+  } else if (e->type == ast_expression_type::CONDITIONAL_EXPRESSION) {
+    double left =  _eval(e->left, param_defs);
+    double right = _eval(e->right, param_defs);
+    double cond = _eval(e->aux, param_defs);
+    return cond?left:right;
   }
 
   eval_error = true;
@@ -121,11 +164,6 @@ double VerilogConstantExprEval::Eval(ast_expression* _s) {
   return val;
 }
 
-static void* ast_list_get_not_null(ast_list* list, unsigned int item) {
-  void* ret = ast_list_get(list, item);
-  ILA_NOT_NULL(ret);
-  return ret;
-}
 
 /// parse only the current module's parameter definitions, will update
 /// param_defs

diff --git a/src/vtarget-out/CMakeLists.txt b/src/vtarget-out/CMakeLists.txt
@@ -7,6 +7,10 @@ target_sources(${ILANG_LIB_NAME} PRIVATE
   ${CMAKE_CURRENT_SOURCE_DIR}/var_extract.cc
   ${CMAKE_CURRENT_SOURCE_DIR}/vtarget_gen_impl.cc
   ${CMAKE_CURRENT_SOURCE_DIR}/single_target.cc
+  ${CMAKE_CURRENT_SOURCE_DIR}/single_target_connect.cc
+  ${CMAKE_CURRENT_SOURCE_DIR}/single_target_misc.cc
+  ${CMAKE_CURRENT_SOURCE_DIR}/single_target_cond.cc
+  ${CMAKE_CURRENT_SOURCE_DIR}/single_target_inv_syn_support.cc
   ${CMAKE_CURRENT_SOURCE_DIR}/vtarget_gen_cosa.cc
   ${CMAKE_CURRENT_SOURCE_DIR}/vtarget_gen_jasper.cc
   ${CMAKE_CURRENT_SOURCE_DIR}/vtarget_gen.cc