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Add make-and-makefile.md for Linux driver development documentation
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id: "make-and-makefile" | ||
title: "Make and Makefile" | ||
tags: ["make", "makefile"] | ||
--- | ||
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## Make | ||
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`make` is a automation tool that helps we to executing commands in a more organized way. It is used to compile and build large projects, but it can be used for any task that requires executing a series of commands. | ||
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Its usefull when we have a project with multiple files and we need to compile them in a specific order. Instead of compiling each file manually, we can use `make` to automate the process. | ||
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### Usage | ||
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```bash | ||
make [target] | ||
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# passing a Makefile | ||
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make -f /foo/bar/Makefile [target] | ||
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``` | ||
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## Makefile | ||
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A `Makefile` is a file that contains a set of rules used by `make`. | ||
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### Syntax | ||
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```makefile | ||
target: dependencies | ||
command | ||
``` | ||
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- `target`: The name of the target to be executed. | ||
- `dependencies`: The files or targets that the target depends on. If any of the dependencies are newer than the target, the command will be executed. | ||
- `command`: The command to be executed. | ||
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### Example | ||
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```makefile | ||
hello: hello.c | ||
gcc -o hello hello.c | ||
``` | ||
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In this example, we have a target called `hello` that depends on the file `hello.c`. The command `gcc -o hello hello.c` is executed to compile the `hello.c` file. | ||
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### Variables | ||
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Variables can be defined in a `Makefile` to store values that can be reused throughout the file. | ||
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```makefile | ||
CC = gcc | ||
CFLAGS = -Wall -Wextra | ||
PATH += /usr/local/bin # append to PATH | ||
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hello: hello.c | ||
$(CC) $(CFLAGS) -o hello hello.c | ||
``` |