Merge pull request #192 from PandABlocks/fmc-panda-sync

Allow capability of adding additional SFP ports through FMC card.

apps/PandABox-fmc_lback-sfp_lback.app.ini

@@ -22,3 +22,8 @@ site: sfp 2
 [SFP3_LBACK]
 module: sfp_loopback
 site: sfp 3
+
+[SFP4_LBACK]
+module: sfp_loopback
+site: fmc_mgt 1
+

common/hdl/defines/interface_types.vhd

@@ -0,0 +1,110 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package interface_types is
+
+    -- FMC Block Record declarations
+
+    type FMC_interface is
+      record
+        FMC_PRSNT       : std_logic_vector(1 downto 0);
+        FMC_LA_P        : std_logic_vector(33 downto 0);
+        FMC_LA_N        : std_logic_vector(33 downto 0);
+        FMC_CLK0_M2C_P  : std_logic;
+        FMC_CLK0_M2C_N  : std_logic;
+        FMC_CLK1_M2C_P  : std_logic;
+        FMC_CLK1_M2C_N  : std_logic;
+      end record FMC_interface;
+
+    view FMC_Module of FMC_interface is
+        FMC_PRSNT       : in;
+        FMC_LA_P        : inout;
+        FMC_LA_N        : inout;
+        FMC_CLK0_M2C_P  : inout;
+        FMC_CLK0_M2C_N  : inout;
+        FMC_CLK1_M2C_P  : in;
+        FMC_CLK1_M2C_N  : in;
+    end view FMC_Module;
+
+    constant FMC_init : FMC_interface;
+
+    type FMC_array is array (natural range <>) of FMC_interface;
+
+    type FMC_ARR_REC is record
+        FMC_ARR : FMC_array;
+    end record FMC_ARR_REC;
+
+    view FMC_MOD_ARR of FMC_ARR_REC is
+        FMC_ARR: view (FMC_Module);
+    end view;
+
+    -- SFP Block Record declarations
+
+    type MGT_interface is
+      record
+        SFP_LOS     : std_logic;
+        GTREFCLK    : std_logic;
+        RXN_IN      : std_logic;
+        RXP_IN      : std_logic;
+        TXN_OUT     : std_logic;
+        TXP_OUT     : std_logic;
+        MGT_REC_CLK : std_logic;
+        LINK_UP     : std_logic;
+        TS_SEC      : std_logic_vector(31 downto 0);
+        TS_TICKS    : std_logic_vector(31 downto 0);
+        MAC_ADDR    : std_logic_vector(47 downto 0);
+        MAC_ADDR_WS : std_logic;
+      end record MGT_interface;
+
+    view MGT_Module of MGT_interface is
+        SFP_LOS     : in;
+        GTREFCLK    : in;
+        RXN_IN      : in;
+        RXP_IN      : in;
+        TXN_OUT     : out;
+        TXP_OUT     : out;
+        MGT_REC_CLK : out;
+        LINK_UP     : out;
+        TS_SEC      : out;
+        TS_TICKS    : out;
+        MAC_ADDR    : in;
+        MAC_ADDR_WS : in;
+    end view MGT_Module;
+
+    constant MGT_init : MGT_interface;
+
+    type MGT_array is array (natural range <>) of MGT_interface;
+
+    type MGT_ARR_REC is record
+        MGT_ARR : MGT_array;
+    end record MGT_ARR_REC;
+
+    view MGT_MOD_ARR of MGT_ARR_REC is
+        MGT_ARR: view (MGT_Module);
+    end view;
+end;
+
+package body interface_types is
+
+    constant FMC_init : FMC_interface := (  FMC_PRSNT => "00",
+                                            FMC_LA_P => (others => 'Z'),
+                                            FMC_LA_N => (others => 'Z'),
+                                            FMC_CLK0_M2C_P => 'Z',
+                                            FMC_CLK0_M2C_N => 'Z',
+                                            FMC_CLK1_M2C_P => '0',
+                                            FMC_CLK1_M2C_N => '0');
+
+    constant MGT_init : MGT_interface := (  SFP_LOS => '0',
+                                            GTREFCLK => '0',
+                                            RXN_IN => '0',
+                                            RXP_IN => '0',
+                                            TXN_OUT => 'Z',
+                                            TXP_OUT => 'Z',
+                                            MGT_REC_CLK => '0',
+                                            LINK_UP => '0',
+                                            TS_SEC => (others => '0'),
+                                            TS_TICKS => (others => '0'),
+                                            MAC_ADDR => (others => '0'),
+                                            MAC_ADDR_WS => '0');
+
+end;

common/hdl/defines/top_defines.vhd

@@ -62,76 +62,7 @@ end record;
 --
 -- TYPEs :
 --
-
--- FMC Block Record declarations
-
-type FMC_input_interface is
-  record
-    EXTCLK          : std_logic;
-    FMC_PRSNT       : std_logic;
-    FMC_CLK1_M2C_P  : std_logic;
-    FMC_CLK1_M2C_N  : std_logic;
-    GTREFCLK        : std_logic;
-    RXP_IN          : std_logic;
-    RXN_IN          : std_logic;
-    MAC_ADDR        : std_logic_vector(47 downto 0);
-    MAC_ADDR_WS     : std_logic;
-  end record FMC_input_interface;
-
-type FMC_inout_interface is
-  record
-    FMC_LA_P        : std_logic_vector(33 downto 0);
-    FMC_LA_N        : std_logic_vector(33 downto 0);
-    FMC_CLK0_M2C_P  : std_logic;
-    FMC_CLK0_M2C_N  : std_logic;
-  end record FMC_inout_interface;
-
-constant FMC_io_init : FMC_inout_interface := (FMC_LA_P => (others => 'Z'),
-                                               FMC_LA_N => (others => 'Z'),
-                                               FMC_CLK0_M2C_P => 'Z',
-                                               FMC_CLK0_M2C_N => 'Z');
-
-type FMC_output_interface is
-  record
-    TXP_OUT         : std_logic;
-    TXN_OUT         : std_logic;
-  end record FMC_output_interface;
-
-constant FMC_o_init : FMC_output_interface := (TXP_OUT => 'Z',
-                                               TXN_OUT => 'Z');
-
--- SFP Block Record declarations
-
-type SFP_input_interface is
-  record
-    SFP_LOS     : std_logic;
-    GTREFCLK    : std_logic;
-    RXN_IN      : std_logic;
-    RXP_IN      : std_logic;
-    MAC_ADDR    : std_logic_vector(47 downto 0);
-    MAC_ADDR_WS : std_logic;
-    MGT_CLK_SEL : std_logic;
-  end record SFP_input_interface;
-
-type SFP_output_interface is
-  record
-    TXN_OUT     : std_logic;
-    TXP_OUT     : std_logic;
-    MGT_REC_CLK : std_logic;
-    LINK_UP     : std_logic;
-    TS_SEC      : std_logic_vector(31 downto 0);
-    TS_TICKS    : std_logic_vector(31 downto 0);
-  end record SFP_output_interface;
-
-constant SFP_o_init : SFP_output_interface := (TXN_OUT => 'Z',
-                                               TXP_OUT => 'Z',
-                                               MGT_REC_CLK => '0',
-                                               LINK_UP => '0',
-                                               TS_SEC => (others => '0'),
-                                               TS_TICKS => (others => '0')
-);
-
-
+
 type seq_t is
 record
     repeats     : unsigned(15 downto 0);
@@ -151,6 +82,9 @@ record
 end record;
 type slow_packet_array is array(natural range <>) of slow_packet;
 
+-- Unconstrained array of std_logic_vector
+type std_uarray is array(natural range <>) of std_logic_vector;
+
 subtype std2_t is std_logic_vector(1 downto 0);
 type std2_array is array(natural range <>) of std2_t;
 

common/hdl/reg_top.vhd

@@ -29,8 +29,7 @@ use work.version.all; -- are not treated as blocks and cannot be autogend
 
 entity reg_top is
 generic (
-    NUM_SFP            : natural := 0;
-    NUM_FMC            : natural := 0
+    NUM_MGT            : natural := 0
 );
 port (
     -- Clock and Reset
@@ -52,10 +51,8 @@ port (
     TS_SEC              : in  std_logic_vector(31 downto 0);
     TS_TICKS            : in  std_logic_vector(31 downto 0);
     -- Output signals
-    SFP_MAC_ADDR        : out std32_array(2*NUM_SFP -1 downto 0) := (others => (others => '1'));
-    SFP_MAC_ADDR_WSTB   : out std_logic_vector(2*NUM_SFP downto 0) := (others => '0');
-    FMC_MAC_ADDR        : out std32_array(2*NUM_FMC -1 downto 0) := (others => (others => '1'));
-    FMC_MAC_ADDR_WSTB   : out std_logic_vector(2*NUM_FMC downto 0) := (others => '0')
+    MGT_MAC_ADDR        : out std32_array(2*NUM_MGT -1 downto 0) := (others => (others => '1'));
+    MGT_MAC_ADDR_WSTB   : out std_logic_vector(2*NUM_MGT downto 0) := (others => '0')
 );
 end reg_top;
 
@@ -100,21 +97,21 @@ begin
     if rising_edge(clk_i) then
         BIT_READ_RST <= '0';
         POS_READ_RST <= '0';
-        if (NUM_SFP > 0 ) then
-            SFP_MAC_ADDR_WSTB(0) <= '0';
-            SFP_MAC_ADDR_WSTB(1) <= '0';
+        if (NUM_MGT > 0 ) then
+            MGT_MAC_ADDR_WSTB(0) <= '0';
+            MGT_MAC_ADDR_WSTB(1) <= '0';
         end if;
-        if (NUM_SFP > 1) then
-            SFP_MAC_ADDR_WSTB(2) <= '0';
-            SFP_MAC_ADDR_WSTB(3) <= '0';
+        if (NUM_MGT > 1) then
+            MGT_MAC_ADDR_WSTB(2) <= '0';
+            MGT_MAC_ADDR_WSTB(3) <= '0';
         end if;
-        if (NUM_SFP > 2 ) then
-            SFP_MAC_ADDR_WSTB(4) <= '0';
-            SFP_MAC_ADDR_WSTB(5) <= '0';
+        if (NUM_MGT > 2 ) then
+            MGT_MAC_ADDR_WSTB(4) <= '0';
+            MGT_MAC_ADDR_WSTB(5) <= '0';
         end if;
-        if (NUM_FMC > 0 ) then
-            FMC_MAC_ADDR_WSTB(0) <= '0';
-            FMC_MAC_ADDR_WSTB(1) <= '0';
+        if (NUM_MGT > 3 ) then
+            MGT_MAC_ADDR_WSTB(6) <= '0';
+            MGT_MAC_ADDR_WSTB(7) <= '0';
         end if;
         if (write_strobe_i = '1') then
             -- System Bus Read Start
@@ -126,44 +123,44 @@ begin
                 POS_READ_RST <= '1';
             end if;
             -- Write MGT MAC addresses
-            if (NUM_SFP > 0) then
+            if (NUM_MGT > 0) then
                 if (write_address = REG_MAC_ADDRESS_BASE_0) then
-                    SFP_MAC_ADDR(0) <= write_data_i;
-                    SFP_MAC_ADDR_WSTB(0) <= '1';
+                    MGT_MAC_ADDR(0) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(0) <= '1';
                 end if;
                 if (write_address = REG_MAC_ADDRESS_BASE_1) then
-                    SFP_MAC_ADDR(1) <= write_data_i;
-                    SFP_MAC_ADDR_WSTB(1) <= '1';
+                    MGT_MAC_ADDR(1) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(1) <= '1';
                 end if;
             end if;
-            if (NUM_SFP > 1) then
+            if (NUM_MGT > 1) then
                 if (write_address = REG_MAC_ADDRESS_BASE_2) then
-                    SFP_MAC_ADDR(2) <= write_data_i;
-                    SFP_MAC_ADDR_WSTB(2) <= '1';
+                    MGT_MAC_ADDR(2) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(2) <= '1';
                 end if;
                 if (write_address = REG_MAC_ADDRESS_BASE_3) then
-                    SFP_MAC_ADDR(3) <= write_data_i;
-                    SFP_MAC_ADDR_WSTB(3) <= '1';
+                    MGT_MAC_ADDR(3) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(3) <= '1';
                 end if;
             end if;
-            if (NUM_SFP > 2) then
+            if (NUM_MGT > 2) then
                 if (write_address = REG_MAC_ADDRESS_BASE_4) then
-                    SFP_MAC_ADDR(4) <= write_data_i;
-                    SFP_MAC_ADDR_WSTB(4) <= '1';
+                    MGT_MAC_ADDR(4) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(4) <= '1';
                 end if;
                 if (write_address = REG_MAC_ADDRESS_BASE_5) then
-                    SFP_MAC_ADDR(5) <= write_data_i;
-                    SFP_MAC_ADDR_WSTB(5) <= '1';
+                    MGT_MAC_ADDR(5) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(5) <= '1';
                 end if;
             end if;
-            if (NUM_FMC > 0) then
+            if (NUM_MGT > 3) then
                 if (write_address = REG_MAC_ADDRESS_BASE_6) then
-                    FMC_MAC_ADDR(0) <= write_data_i;
-                    FMC_MAC_ADDR_WSTB(0) <= '1';
+                    MGT_MAC_ADDR(6) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(6) <= '1';
                 end if;
                 if (write_address = REG_MAC_ADDRESS_BASE_7) then
-                    FMC_MAC_ADDR(1) <= write_data_i;
-                    FMC_MAC_ADDR_WSTB(1) <= '1';
+                    MGT_MAC_ADDR(7) <= write_data_i;
+                    MGT_MAC_ADDR_WSTB(7) <= '1';
                 end if;
            end if;
         end if;