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Dpdk #11

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Dpdk #11

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20280bd
First push for gw-move-to-2023
GregWatson Sep 27, 2023
aa59614
Updated constraints. Now have clean build of reference-switch. Timing…
GregWatson Dec 3, 2023
64906a4
Added Zhukun's patch to fix driver for recent kernels
GregWatson Dec 8, 2023
4cf84e4
Merge remote-tracking branch 'refs/remotes/origin/gw-move-to-2023' in…
GregWatson Dec 8, 2023
a0186c0
Started to create project reference_dma and module nf_data_sink_v1_0_0
GregWatson Jan 22, 2024
feead6d
updated opennic-driver.patch
GregWatson Jan 24, 2024
7192053
Simple send_pkt using scapy
GregWatson Jan 26, 2024
6098052
Modified nf_data_sink_v1_0_0 to have measure pkts, bytes amd time
GregWatson Jan 30, 2024
f2a3739
Updated reference_dma to get simulation working.
GregWatson Feb 4, 2024
a578440
Starting on packet generator C program.
GregWatson Feb 14, 2024
10b39be
Merge remote-tracking branch 'refs/remotes/origin/dma_perf_explore' i…
GregWatson Feb 14, 2024
fbce186
Created pkt_Send C program.
GregWatson Feb 19, 2024
3b817ef
Added new regs for nf_data_sink to measure clock frequencies
GregWatson Feb 22, 2024
906ee64
Added tkeep_last regs to see final bytes.
GregWatson Feb 26, 2024
c601b19
Push
GregWatson Feb 26, 2024
66c3b03
Push
GregWatson Feb 26, 2024
6811314
Seems to coubnt pkts and bytes correctly. Need to optimize pkt send.
GregWatson Feb 27, 2024
15ba616
Updated pkt_send app to measure performance over range of packet sizes.
GregWatson Mar 6, 2024
1f88fca
Added logic to preevnt datapath from being deleted.
GregWatson Mar 7, 2024
33a4344
Merge branch 'dma_perf_explore' of github.com:GregWatson/NetFPGA-PLUS…
GregWatson Mar 7, 2024
e099245
Added constant amount of data (-R) mode, per Noa's suggestion.
GregWatson Mar 12, 2024
9c04c2e
Merge branch 'dma_perf_explore' of github.com:GregWatson/NetFPGA-PLUS…
GregWatson Mar 12, 2024
8aa4fc4
Update for DPDK branch. Needed to move to other computer.
GregWatson Apr 3, 2024
5e19bb8
Merge branch 'main' into dpdk
GregWatson Apr 3, 2024
dad8702
Modified qdma_testapp to NOT read file, but just read from mbufs (wha…
GregWatson Apr 5, 2024
a4209ff
Syntax fix
GregWatson Apr 5, 2024
0e718df
Added module ID reporting
GregWatson Apr 5, 2024
e304a7f
Adding missing lib
GregWatson Apr 5, 2024
1f49a80
Added missing files to commit.
GregWatson Apr 5, 2024
4867a94
Merge branch 'dpdk' of github.com:GregWatson/NetFPGA-PLUS-GW into dpdk
GregWatson Apr 5, 2024
d1f6afd
Added stats sampling code
GregWatson Apr 5, 2024
a90d64a
Modified qdma-testapp trying to see why no data is moved tthrough the…
GregWatson Apr 13, 2024
dd64bf0
trying to build under DPDK - registers for nf_data_sink do not appear…
GregWatson May 7, 2024
363d072
Needed for build. Really these should be auto-generated by the flow.
GregWatson Jun 30, 2024
ead368e
App update
GregWatson Jul 11, 2024
20ce70c
pull from origin
GregWatson Jul 11, 2024
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1 change: 1 addition & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,7 @@ cores:
make -C $(LIB_HW_DIR)/contrib/nf_endianess_manager_v1_0_0/
make -C $(LIB_HW_DIR)/std/axis_fifo_v1_0_0/
make -C $(LIB_HW_DIR)/std/nf_axis_converter_v1_0_0/
make -C $(LIB_HW_DIR)/std/nf_data_sink_v1_0_0/
make -C $(LIB_HW_DIR)/std/nf_mac_attachment_v1_0_0/
make -C $(LIB_HW_DIR)/std/input_arbiter_v1_0_0/
make -C $(LIB_HW_DIR)/std/output_queues_v1_0_0/
Expand Down
9 changes: 5 additions & 4 deletions hw/lib/common/hdl/top.v
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module top #(
parameter SIMULATIOM = "FALSE",
parameter BOARD = "AU280",
parameter BOARD = "AU250", // Greg: was "AU280"
parameter C_NF_DATA_WIDTH = 512 ,
parameter C_NF_TUSER_WIDTH = 128,
parameter C_IF_DATA_WIDTH = 512,
Expand Down Expand Up @@ -183,6 +183,10 @@ module top #(
end
end

// Moved instantiation here to remove synth warning
wire core_clk;
wire locked;

reg [9:0] core_rst_cnt = 10'd0;
reg core_rst_reg;
always @ (posedge core_clk) begin
Expand All @@ -199,9 +203,6 @@ module top #(
wire axis_aclk, axil_aclk_250m;
wire axis_rst, axil_rst_250m;

wire core_clk;
wire locked;

clk_wiz_1 u_clk_wiz_1 (
.clk_out1(core_clk),
.reset (axis_rst),
Expand Down
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