This repository is meant for learning some concepts of UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a Arithmetic Logic Unit to perform calculations with values stored in registers through a register bank.
This project is capable of performing functional verification of a ALU (Arithmetic Logic Unit) developed in Systemverilog by creating a verification environment developed according to the UVM methodology.
Systemverilog
UVM
Functional Verification
Multiple Clock Domains
Virtual Sequences
Clocking Blocks
You can download the project's source code.
The Makefile in the tb/rundir/
directory has the following options:
make sim
: Run the project with Xcelium Logic Simulator from Cadence;make gui
: Run the simulation using Simvision's GUI.
When you run base_test
you should notice at the end of the log 10000 matches with the reference model 🏆
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