Add core_name param

* Parse YAML from TANDEM * Add marchid and vendorid * Bump core-v-verif * Check if YAML exist and report * EOT Wait for spike tandem to finish * Change to new RVFI implementation * Add missing disabled fields when RVS and RVU
MarioOpenHWGroup · Apr 24, 2024 · 929df56 · 929df56
1 parent 8a9d7a8
commit 929df56
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Showing 13 changed files with 168 additions and 84 deletions.
diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -773,7 +773,7 @@ module csr_regfile
           // -> last bit of pmpaddr must be set 0/1 based on the mode:
           // NA4, NAPOT: 1
           // TOR, OFF:   0
-          if (pmpcfg_q[index].addr_mode[1] == 1'b1) csr_rdata = pmpaddr_q[index][CVA6Cfg.PLEN-3:0];
+          if (pmpcfg_q[index].addr_mode[1] == 1'b1 || pmpcfg_q[index].addr_mode == 'h0) csr_rdata = pmpaddr_q[index][CVA6Cfg.PLEN-3:0];
           else csr_rdata = {pmpaddr_q[index][CVA6Cfg.PLEN-3:1], 1'b0};
         end
         default: read_access_exception = 1'b1;
@@ -1249,6 +1249,18 @@ module csr_regfile
           if (!CVA6Cfg.RVV) begin
             mstatus_d.vs = riscv::Off;
           end
+          if (!CVA6Cfg.RVS) begin
+            mstatus_d.sie = riscv::Off;
+            mstatus_d.spie = riscv::Off;
+            mstatus_d.spp = riscv::Off;
+            mstatus_d.sum = riscv::Off;
+            mstatus_d.mxr = riscv::Off;
+            mstatus_d.tvm = riscv::Off;
+            mstatus_d.tsr = riscv::Off;
+          end
+          if (!CVA6Cfg.RVU) begin
+            mstatus_d.mprv = riscv::Off;
+          end
           // If h-extension is not enabled, priv level HS is reserved
           if (!CVA6Cfg.RVH) begin
             if (mstatus_d.mpp == riscv::PRIV_LVL_HS) begin

diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv
@@ -322,7 +322,8 @@ module cva6_rvfi
 
   `CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended)
 
-  `CONNECT_RVFI_FULL(1'b1, mstatush, '0)
+  bit [31:0] mstatush_q;
+    `CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q)
 
   `CONNECT_RVFI_FULL(1'b1, misa, IsaCode)
 

diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv
@@ -65,6 +65,8 @@ module ariane_testharness #(
   logic        init_done;
   logic [31:0] jtag_exit, dmi_exit;
   logic [31:0] rvfi_exit;
+  logic [31:0] tracer_exit;
+  logic [31:0] tandem_exit;
 
   logic        jtag_TCK;
   logic        jtag_TMS;
@@ -700,7 +702,7 @@ module ariane_testharness #(
     .rst_ni(rst_ni),
     .rvfi_i(rvfi_instr),
     .rvfi_csr_i(rvfi_csr),
-    .end_of_test_o(rvfi_exit)
+    .end_of_test_o(tracer_exit)
   );
 
 `ifdef SPIKE_TANDEM
@@ -713,11 +715,19 @@ module ariane_testharness #(
         .rst_ni,
         .clint_tick_i   ( rtc_i    ),
         .rvfi_i         ( rvfi_instr ),
-        .rvfi_csr_i     ( rvfi_csr )
+        .rvfi_csr_i     ( rvfi_csr ),
+        .end_of_test_o  ( tandem_exit )
     );
     initial begin
         $display("Running binary in tandem mode");
     end
+    always_ff @(posedge clk_i) begin
+        if (tandem_exit) begin
+            rvfi_exit <= tracer_exit;
+        end
+    end
+`else
+    assign rvfi_exit = tracer_exit;
 `endif
 
 `ifdef VERILATOR

diff --git a/corev_apu/tb/common/spike.sv b/corev_apu/tb/common/spike.sv
@@ -41,12 +41,14 @@ module spike #(
     input logic                                     rst_ni,
     input logic                                     clint_tick_i,
     input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0]   rvfi_i,
-    input rvfi_csr_t                                rvfi_csr_i
+    input rvfi_csr_t                                rvfi_csr_i,
+    output logic[31:0]                              end_of_test_o
 );
     string binary = "";
     string rtl_isa = "";
 
     st_core_cntrl_cfg st;
+    bit sim_finished;
 
     initial begin
         string core_name = "cva6";
@@ -73,18 +75,18 @@ module spike #(
     st_rvfi s_core [CVA6Cfg.NrCommitPorts-1:0];
     bit core_valid [CVA6Cfg.NrCommitPorts-1:0];
 
-    `define GET_RVFI_CSR(CSR_ADDR, CSR_NAME, CSR_INDEX) \
-        s_core[i].csr_valid[CSR_INDEX] <= 1; \
-        s_core[i].csr_addr [CSR_INDEX] <= CSR_ADDR;\
-        s_core[i].csr_rdata[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.rdata;\
-        s_core[i].csr_rmask[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.rmask;\
-        s_core[i].csr_wdata[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.wdata;\
-        s_core[i].csr_wmask[CSR_INDEX] <= rvfi_csr_i.``CSR_NAME``.wmask;\
+    `define GET_RVFI_CSR(CSR_ADDR, CSR_NAME) \
+        s_core[i].csr_valid[CSR_ADDR] <= 1; \
+        s_core[i].csr_addr [CSR_ADDR] <= CSR_ADDR;\
+        s_core[i].csr_rdata[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.rdata;\
+        s_core[i].csr_rmask[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.rmask;\
+        s_core[i].csr_wdata[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.wdata;\
+        s_core[i].csr_wmask[CSR_ADDR] <= rvfi_csr_i.``CSR_NAME``.wmask;
 
     always_ff @(posedge clk_i) begin
         if (rst_ni) begin
 
-            for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
+            for (int i = 0; i < CVA6Cfg.NrCommitPorts && !sim_finished; i++) begin
 
                 if (rvfi_i[i].valid || rvfi_i[i].trap) begin
                     core_valid[i] <= 1;
@@ -111,40 +113,50 @@ module spike #(
                     s_core[i].mem_wdata  <= rvfi_i[i].mem_wdata;
 
 
-                    `GET_RVFI_CSR (CSR_MSTATUS      , mstatus     ,  0)
-                    `GET_RVFI_CSR (CSR_MCAUSE       , mcause      ,  1)
-                    `GET_RVFI_CSR (CSR_MEPC         , mepc        ,  2)
-                    `GET_RVFI_CSR (CSR_MTVEC        , mtvec       ,  3)
-                    `GET_RVFI_CSR (CSR_MISA         , misa        ,  4)
-                    `GET_RVFI_CSR (CSR_MTVAL        , mtval       ,  5)
-                    `GET_RVFI_CSR (CSR_MIDELEG      , mideleg     ,  6)
-                    `GET_RVFI_CSR (CSR_MEDELEG      , medeleg     ,  7)
-                    `GET_RVFI_CSR (CSR_SATP         , satp        ,  8)
-                    `GET_RVFI_CSR (CSR_MIE          , mie         ,  9)
-                    `GET_RVFI_CSR (CSR_STVEC        , stvec       , 10)
-                    `GET_RVFI_CSR (CSR_SSCRATCH     , sscratch    , 11)
-                    `GET_RVFI_CSR (CSR_SEPC         , sepc        , 12)
-                    `GET_RVFI_CSR (CSR_MSCRATCH     , mscratch    , 13)
-                    `GET_RVFI_CSR (CSR_STVAL        , stval       , 14)
-                    `GET_RVFI_CSR (CSR_SCAUSE       , scause      , 15)
-                    `GET_RVFI_CSR (CSR_PMPCFG0      , pmpcfg0     , 16)
-                    `GET_RVFI_CSR (CSR_PMPCFG1      , pmpcfg1     , 17)
-                    `GET_RVFI_CSR (CSR_PMPCFG2      , pmpcfg2     , 18)
-                    `GET_RVFI_CSR (CSR_PMPCFG3      , pmpcfg3     , 19)
+                    `GET_RVFI_CSR (CSR_MSTATUS      , mstatus     )
+                    `GET_RVFI_CSR (CSR_MCAUSE       , mcause      )
+                    `GET_RVFI_CSR (CSR_MEPC         , mepc        )
+                    `GET_RVFI_CSR (CSR_MTVEC        , mtvec       )
+                    `GET_RVFI_CSR (CSR_MISA         , misa        )
+                    `GET_RVFI_CSR (CSR_MTVAL        , mtval       )
+                    `GET_RVFI_CSR (CSR_MIDELEG      , mideleg     )
+                    `GET_RVFI_CSR (CSR_MEDELEG      , medeleg     )
+                    `GET_RVFI_CSR (CSR_SATP         , satp        )
+                    `GET_RVFI_CSR (CSR_MIE          , mie         )
+                    `GET_RVFI_CSR (CSR_STVEC        , stvec       )
+                    `GET_RVFI_CSR (CSR_SSCRATCH     , sscratch    )
+                    `GET_RVFI_CSR (CSR_SEPC         , sepc        )
+                    `GET_RVFI_CSR (CSR_MSCRATCH     , mscratch    )
+                    `GET_RVFI_CSR (CSR_STVAL        , stval       )
+                    `GET_RVFI_CSR (CSR_SCAUSE       , scause      )
+                    `GET_RVFI_CSR (CSR_PMPCFG0      , pmpcfg0     )
+                    `GET_RVFI_CSR (CSR_PMPCFG1      , pmpcfg1     )
+                    `GET_RVFI_CSR (CSR_PMPCFG2      , pmpcfg2     )
+                    `GET_RVFI_CSR (CSR_PMPCFG3      , pmpcfg3     )
                     for (int j = 0; j < 16; j++) begin
-                    `GET_RVFI_CSR (CSR_PMPADDR0 + j  , pmpaddr[j]  , 20 + j)
+                        `GET_RVFI_CSR (CSR_PMPADDR0 + j  , pmpaddr[j])
                     end
-                    `GET_RVFI_CSR (CSR_MINSTRET     , instret     , 37)
+                    `GET_RVFI_CSR (CSR_MINSTRET     , instret     )
+                    `GET_RVFI_CSR (CSR_MINSTRETH    , instreth    )
+                    `GET_RVFI_CSR (CSR_MSTATUSH     , mstatush    )
+                    `GET_RVFI_CSR (CSR_MIP          , mip         )
+                    `GET_RVFI_CSR (CSR_MCYCLE       , mcycle      )
                 end
                 else begin
                     core_valid[i] <= 0;
                 end
+            end
 
+            for (int i = 0; i < CVA6Cfg.NrCommitPorts && !sim_finished; i++) begin
                 if (core_valid[i]) begin
                     st_rvfi core, reference_model;
                     core = s_core[i];
+
                     rvfi_spike_step(core, reference_model);
                     rvfi_compare(core, reference_model);
+
+                    end_of_test_o = reference_model.halt;
+                    sim_finished = reference_model.halt[0];
                 end
             end
         end

diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv
@@ -70,8 +70,9 @@ module rvfi_tracer #(
   logic[31:0] end_of_test_d;
 
   assign end_of_test_o = end_of_test_d;
+
   always_ff @(posedge clk_i) begin
-    end_of_test_q = (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
+    end_of_test_q <= (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
     for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
       pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
       // print the instruction information if the instruction is valid or a trap is taken
@@ -111,7 +112,7 @@ module rvfi_tracer #(
             if (TOHOST_ADDR != '0 &&
                 rvfi_i[i].mem_paddr == TOHOST_ADDR &&
                 rvfi_i[i].mem_wdata[0] == 1'b1) begin
-              end_of_test_q = rvfi_i[i].mem_wdata[31:0];
+              end_of_test_q <= rvfi_i[i].mem_wdata[31:0];
             end
           end
         end
@@ -138,7 +139,7 @@ module rvfi_tracer #(
     else
       cycles <= cycles+1;
     if (cycles > SIM_FINISH)
-      end_of_test_q = 32'hffff_ffff;
+      end_of_test_q <= 32'hffff_ffff;
 
     end_of_test_d <= end_of_test_q;
   end

diff --git a/verif/core-v-verif b/verif/core-v-verif
diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv
@@ -236,6 +236,8 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg");
    isacov_cfg.core_cfg = this;
    rvfi_cfg.core_cfg = this;
 
+   $value$plusargs("core_name=%s", this.core_name);
+
 endfunction : new
 
 function void uvme_cva6_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt);

diff --git a/verif/sim/Makefile b/verif/sim/Makefile
@@ -124,42 +124,6 @@ spike:
 		$(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant) --priv=$(priv) $(spike_params) -l $(elf)
 	cp $(log).iss $(log)
 
-###############################################################################
-# testharness specific commands, variables
-###############################################################################
-vcs-testharness:
-	make -C $(path_var) work-dpi/ariane_dpi.so
-	make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts))$(if $(spike-tandem),SPIKE_TANDEM=1)
-	$(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/util/init_testharness.do,) +permissive \
-	  +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
-	  +elf_file=$(elf) +permissive-off ++$(elf) $(issrun_opts)  \
-	  $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm) \
-	  $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv) \
-	  -sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr
-	# TODO: Add support for waveform collection.
-	# Generate disassembled log.
-	$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
-	grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
-
-veri-testharness:
-	make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
-	$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
-	  $(COMMON_PLUS_ARGS)
-	# If present, move default waveform files to log directory.
-	# Keep track of target in waveform file name.
-	[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
-	[ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.vcd
-	# Generate disassembled log.
-	$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
-	grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
-
-questa-testharness:
-	mkdir -p $(path_var)/tmp
-	make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)) batch-mode=1 elf_file=$(elf) \
-	# TODO: Add support for waveform collection.
-	$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
-	grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm
-
 ###############################################################################
 # UVM specific commands, variables
 ###############################################################################
@@ -210,13 +174,14 @@ COMMON_PLUS_ARGS = \
 	++$(elf) \
 	+elf_file=$(elf) \
 	+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
-	+signature=$(elf).signature_output  +UVM_TESTNAME=uvmt_cva6_firmware_test_c
+	+signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c \
+	+report_file=$(log).yaml +core_name=$(target)
 
 ifneq ($(UVM_VERBOSITY),)
 COMMON_PLUS_ARGS += +UVM_VERBOSITY=$(UVM_VERBOSITY)
 endif
 
-COMMON_RUN_UVM_FLAGS = \
+COMMON_RUN_FLAGS = \
 	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
 	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
 	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
@@ -249,9 +214,9 @@ ifneq ($(DEBUG),)               # If RTL DEBUG support requested
 endif
 
 ifneq ($(SPIKE_TANDEM),)
-COMMON_RUN_UVM_FLAGS += +scoreboard_enabled=1
+COMMON_RUN_FLAGS += +scoreboard_enabled=1
 else
-COMMON_RUN_UVM_FLAGS += +scoreboard_enabled=0
+COMMON_RUN_FLAGS += +scoreboard_enabled=0
 endif
 
 vcs_uvm_comp:
@@ -267,7 +232,7 @@ vcs_uvm_run:
 	$(if $(TRACE_FAST), unset VERDI_HOME ;) \
 	cd $(VCS_WORK_DIR)/ && \
 	$(VCS_WORK_DIR)/simv \
-	    $(COMMON_RUN_UVM_FLAGS) \
+	    $(COMMON_RUN_FLAGS) \
 	    $(ALL_SIMV_UVM_FLAGS) \
 	    $(cov-run-opt) $(issrun_opts)
 
@@ -308,7 +273,7 @@ questa_uvm_comp:
 questa_uvm_run:
 	@echo "[QUESTA] Running Model"
 	vsim -64  \
-	  $(COMMON_RUN_UVM_FLAGS) \
+	  $(COMMON_RUN_FLAGS) \
 	  -sv_lib $(QUESTASIM_HOME)/uvm-1.2/linux_x86_64/uvm_dpi \
 	  -c -do "run -all; " \
 	  -work $(VSIM_WORK_DIR) -t 1ns \
@@ -336,6 +301,39 @@ vcs_clean_all:
 	@echo "[VCS] Cleanup (entire vcs_work dir)"
 	rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart
 
+###############################################################################
+# testharness specific commands, variables
+###############################################################################
+vcs-testharness:
+	make -C $(path_var) work-dpi/ariane_dpi.so
+	make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts))$(if $(spike-tandem),SPIKE_TANDEM=1)
+	$(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/util/init_testharness.do,) +permissive \
+		$(COMMON_RUN_FLAGS) \
+	  +elf_file=$(elf) +permissive-off ++$(elf) $(issrun_opts)  \
+	# TODO: Add support for waveform collection.
+	# Generate disassembled log.
+	$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
+	grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
+
+veri-testharness:
+	make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
+	$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
+	  +elf_file=$(elf) +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) +core_name=$(target) +report_file=$(log).yaml
+	# If present, move default waveform files to log directory.
+	# Keep track of target in waveform file name.
+	[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
+	[ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.vcd
+	# Generate disassembled log.
+	$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
+	grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
+
+questa-testharness:
+	mkdir -p $(path_var)/tmp
+	make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)) batch-mode=1 elf_file=$(elf) \
+	# TODO: Add support for waveform collection.
+	$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
+	grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm
+
 ###############################################################################
 # Common targets and rules
 ###############################################################################