Many corrections

* Undo mcountinhibit
* Add yaml_report for questa-testharness
* Change extensions for cva6
* Erase double cvxif extension activation

Makefile

@@ -277,7 +277,8 @@ vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262
 uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
 questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) \
 			+tohost_addr=$(shell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
-			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579
+			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579 +report_file=$(report_file) \
+			+config_file=$(iss_yaml)
 compile_flag_vhd += -64 -nologo -quiet -2008
 
 # Iterate over all include directories and write them with +incdir+ prefixed

config/gen_from_riscv_config/cv32a65x/spike/spike.yaml

@@ -33,7 +33,6 @@ spike_param_tree:
       tinfo_accessible: 0
       mscontext_accessible: 0
       mcontext_accessible: 0
-      mcountinhibit_accessible: 0
       tdata1_accessible: 0
       tdata2_accessible: 0
       tdata3_accessible: 0

verif/sim/Makefile

@@ -131,10 +131,6 @@ else
 	cov-run-opt  =
 endif
 
-ifdef cvxif
-	spike_extension = --extension=cvxif
-endif
-
 ###############################################################################
 # Spike specific commands, variables
 ###############################################################################
@@ -434,6 +430,7 @@ xrun-testharness:
 questa-testharness:
 	mkdir -p $(path_var)/tmp
 	make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)+core_name=$(target)) batch-mode=1 elf_file=$(elf) \
+	    report_file=$(log).yaml iss_yaml=$(spike_yaml)
 	# TODO: Add support for waveform collection.
 	$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
 	grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm

verif/tb/core/uvma_cva6pkg_utils.sv

@@ -38,7 +38,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     cfg.ext_zicsr_supported = 1;
     cfg.ext_zicntr_supported = 0;
 
-    cfg.ext_cv32a60x_supported = 1;
+    cfg.ext_cv32a60x_supported = 0;
 
     // FIXME TODO: Temporary solution. We need explicit info on memory map.
     // FORNOW The solution below relies on specific region ordering.
@@ -78,7 +78,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
 
     void'(spike_set_param_bool(base, "hide_csrs_based_on_priv", 1));
     void'(spike_set_param_uint64_t(base, "mtvec_vectored_alignment", 64 * 4));
-    void'(spike_set_param_str(base, "extensions", "cv32a60x"));
+    void'(spike_set_param_str(base, "extensions", "cvxif"));
 
     // All enabled except XS and TW bits
     void'(spike_set_param_uint64_t(base, "mstatus_write_mask", 'hFFDE_7FFF));