[TANDEM] CSR Params Refactor + CSR API (openhwgroup#2407)

Makefile

@@ -274,10 +274,15 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
 compile_flag     += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 +permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
 vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262
 
+ifdef config-file
+  spike-yaml-plusarg = +config_file=$(spike_yaml)
+endif
+
 uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
 questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) \
 			+tohost_addr=$(shell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
-			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579
+			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579 +report_file=$(report_file) \
+			$(spike-yaml-plusarg)
 compile_flag_vhd += -64 -nologo -quiet -2008
 
 # Iterate over all include directories and write them with +incdir+ prefixed

config/gen_from_riscv_config/cv32a65x/spike/spike.yaml

@@ -13,14 +13,15 @@ spike_param_tree:
   core_configs:
     -
       isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+      extensions: cv32a60x,cvxif
       boot_addr: 2147483648
-      marchid: 3
-      misa_we: false
-      misa_we_enable: true
+      marchid_override_mask: 0xFFFFFFFF
+      marchid_override_value: 0x3
+      misa_write_mask: 0x0
       pmpaddr0: 0
       pmpcfg0: 0
-      pmpregions: 64
-      usable_pmpregions: 8
+      pmpregions_max: 64
+      pmpregions_writable: 8
       priv: M
       status_fs_field_we: false
       status_fs_field_we_enable: false
@@ -29,4 +30,17 @@ spike_param_tree:
       mstatus_write_mask: 136
       mstatus_override_mask: 6144
       mtval_write_mask: 0
+      tinfo_accessible: 0
+      mscontext_accessible: 0
+      mcontext_accessible: 0
+      tdata1_accessible: 0
+      tdata2_accessible: 0
+      tdata3_accessible: 0
+      tselect_accessible: 0
+      mhartid: 0
+      mvendorid_override_mask : 0xFFFFFFFF
+      mvendorid_override_value: 1538
+      csr_counters_injection: true
       unified_traps: true
+      mcycleh_implemented: false
+      mhpmevent31_implemented: false

verif/regress/install-spike.sh

@@ -52,11 +52,11 @@ if ! [ -f "$SPIKE_INSTALL_DIR/bin/spike" ]; then
   fi
   # Build both shared and static versions of the yaml-cpp library in sequence
   # prior to building Spike.
-  make yaml-cpp-static
-  make yaml-cpp
+  make -j${NUM_JOBS} yaml-cpp-static
+  make -j${NUM_JOBS} yaml-cpp
   make -j${NUM_JOBS}
   echo "Installing Spike in '$SPIKE_INSTALL_DIR'..."
-  make install
+  make -j${NUM_JOBS} install
   cd $CALLER_DIR
 else
   echo "Spike already installed in '$SPIKE_INSTALL_DIR'."

verif/sim/Makefile

@@ -67,6 +67,9 @@ spike_params_final = $(spike_params)
 ifneq ($(wildcard $(spike_yaml)),)
   spike_params_final := $(spike_params_final) --param-file $(spike_yaml)
   spike-yaml-plusarg = +config_file=$(spike_yaml)
+  spike-yaml-makearg = config_file=$(spike_yaml)
+else
+  spike_params_final := $(spike_params_final) --extension=cvxif
 endif
 
 ##############################################
@@ -131,10 +134,6 @@ else
 	cov-run-opt  =
 endif
 
-ifdef cvxif
-	spike_extension = --extension=cvxif
-endif
-
 ###############################################################################
 # Spike specific commands, variables
 ###############################################################################
@@ -434,6 +433,7 @@ xrun-testharness:
 questa-testharness:
 	mkdir -p $(path_var)/tmp
 	make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)+core_name=$(target)) batch-mode=1 elf_file=$(elf) \
+	    report_file=$(log).yaml $(spike-yaml-makearg)
 	# TODO: Add support for waveform collection.
 	$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
 	grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm

verif/tb/core/uvma_cva6pkg_utils.sv

@@ -38,7 +38,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     cfg.ext_zicsr_supported = 1;
     cfg.ext_zicntr_supported = 0;
 
-    cfg.ext_cv32a60x_supported = 1;
+    cfg.ext_cv32a60x_supported = 0;
 
     // FIXME TODO: Temporary solution. We need explicit info on memory map.
     // FORNOW The solution below relies on specific region ordering.
@@ -78,7 +78,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
 
     void'(spike_set_param_bool(base, "hide_csrs_based_on_priv", 1));
     void'(spike_set_param_uint64_t(base, "mtvec_vectored_alignment", 64 * 4));
-    void'(spike_set_param_str(base, "extensions", "cv32a60x"));
+    void'(spike_set_param_str(base, "extensions", "cvxif"));
 
     // All enabled except XS and TW bits
     void'(spike_set_param_uint64_t(base, "mstatus_write_mask", 'hFFDE_7FFF));