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Bump core-v-verif
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@MarioOpenHWGroup
MarioOpenHWGroup committed Aug 19, 2024
1 parent 89eb77a commit 6037e5f
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion verif/core-v-verif
Submodule core-v-verif updated 20 files
+4 −4 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_covg.sv
+4 −4 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_slv_seq.sv
+1 −0 lib/uvm_components/uvmc_rvfi_reference_model/rvfi_spike.sv
+3 −0 mk/Common.mk
+1 −0 mk/uvmt/vcs.mk
+27 −0 vendor/patches/riscv/riscv-isa-sim/0030-fix-csr-injection.patch
+838 −0 vendor/patches/riscv/riscv-isa-sim/0031-csr-refactor-params.patch
+5 −5 vendor/riscv/riscv-isa-sim/Makefile.in
+71 −81 vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+3 −3 vendor/riscv/riscv-isa-sim/riscv/Proc.h
+13 −2 vendor/riscv/riscv-isa-sim/riscv/Simulation.cc
+2 −0 vendor/riscv/riscv-isa-sim/riscv/Simulation.h
+310 −1 vendor/riscv/riscv-isa-sim/riscv/csrs_ext.cc
+11 −0 vendor/riscv/riscv-isa-sim/riscv/csrs_ext.h
+2 −1 vendor/riscv/riscv-isa-sim/riscv/processor.cc
+16 −0 vendor/riscv/riscv-isa-sim/riscv/riscv_dpi.cc
+3 −0 vendor/riscv/riscv-isa-sim/riscv/sim.cc
+2 −2 vendor/riscv/riscv-isa-sim/riscv/sim.h
+10 −3 vendor/riscv/riscv-isa-sim/spike_main/spike-dpi.cc
+1 −0 vendor/riscv/riscv-isa-sim/spike_main/spike_main.mk.in

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