Rob

Makefile

@@ -164,7 +164,7 @@ GREP = grep -E --color=auto
 
 # TODO: add more modules here
 #TESTED_MODULES = mult rob
-TESTED_MODULES = rs
+TESTED_MODULES = rob
 # TODO: add verilog module dependencies here:
 # (do not include header files)
 # Helper function:
@@ -174,10 +174,10 @@ MULT_DEPS = verilog/mult_stage.sv
 $(call DEPS,mult): $(MULT_DEPS)
 
 # No dependencies for the rob (TODO: add any you create)
-ROB_DEPS =
+ROB_DEPS = verilog/rob.sv
 $(call DEPS,rob): $(ROB_DEPS)
 
-RS_DEPS = 
+RS_DEPS = verilog/rs.sv
 $(call DEPS, rs): $(RS_DEPS)
 
 # This allows you to use the following make targets:
@@ -309,15 +309,16 @@ HEADERS = verilog/sys_defs.svh \
 TESTBENCH = test/pipeline_test.sv \
             test/pipeline_print.c \
             test/mem.sv \
-	    test/rs_test.sv
+	    test/rs_test.sv \
+	    test/rob_test.sv
 
 # you could simplify this line with $(wildcard verilog/*.sv) - but the manual way is more explicit
 SOURCES = verilog/pipeline.sv \
           verilog/regfile.sv \
           verilog/icache.sv \
           verilog/mult.sv \
           verilog/mult_stage.sv \
-	  verilog/rs.sv \
+	  verilog/rs.sv 
 
 SYNTH_FILES = synth/pipeline.vg
 

README.md

@@ -1,3 +1,13 @@
 # Triple-O R10K
 
 An out of order processor based on R10K
+
+The modules currently functional are:
+
+`Reservation Station`
+
+`Reorder Buffer`
+
+`Free List`
+
+`MAP Table`

documentation/mapped_vars.MD

@@ -1,3 +1,3 @@
-# define PHYS_REG_SZ (32 + `ROB_SZ)
+## define PHYS_REG_SZ (32 + `ROB_SZ)
 Physical Register for the support of register renaming. 
 

test/map_table_test.sv

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+`include "verilog/sys_defs.svh"
+`include "verilog/ISA.svh"
+
+module map_table_tb;
+
+// Define testbench signals based on the map_table module's interface
+reg clock;
+reg reset;
+reg CDB_enable;
+TAG T, T1, T2, CDB;
+logic write_en;
+reg [4:0] reg_1, reg_2, dest_reg;
+TAG new_tag, T_old;
+
+// Instantiate the map_table
+map_table dut (
+    .clock(clock),
+    .reset(reset),
+    .read_idx_1(reg_1),
+    .read_idx_2(reg_2),
+    .read_out_1(T1),
+    .read_out_2(T2),
+
+    .write_en(write_en),
+    .write_idx(dest_reg),
+    .write_tag(new_tag),
+    .write_out(T_old)
+);
+
+// Clock generation
+initial begin
+    clock = 0;
+    forever #5 clock = ~clock;
+    /*assert property(@(posedge clock) 
+	if(command_inp == READ)
+		T1 && T1_out
+
+	);*/
+end
+
+
+// Test stimulus
+initial begin
+    // Initialize inputs
+
+$display("STARTING TESTBENCH!");
+
+    reset = 1;
+$display("@@@ Time:%4.0f clock:%b reset:%b T1:%b T2:%b reg_1:%b reg_2:%b write_en:%b dest_reg:%b new_tag:%b T_old:%b", $time, clock, reset, T1, T2,reg_1, reg_2, write_en, dest_reg, new_tag, T_old);
+
+$monitor("@@@ Time:%4.0f clock:%b reset:%b T1:%b T2:%b reg_1:%b reg_2:%b write_en:%b dest_reg:%b new_tag:%b T_old:%b", $time, clock, reset, T1, T2,reg_1, reg_2, write_en, dest_reg, new_tag, T_old);
+    // Release reset
+    #10;
+    reset = 0;
+    CDB_enable = 0;
+    // Test read functionality of tags
+    #10;
+    reg_1 = 1;
+    reg_2 = 2;
+
+    #10;
+    reg_1 = 10;
+    reg_2 = 12;
+
+    #10;
+    write_en = 1;
+    dest_reg = 2;
+    new_tag.tag = 5;
+    new_tag.valid = 1;
+    new_tag.valid = 0;
+
+	// Continue simulation for a while to observe behavior
+    #10;
+    $display("\nENDING TESTBENCH: SUCCESS!");
+    $display("@@@ Passed\n");
+    $finish; // End simulation
+end
+
+// Initialize signals for waveform generation
+initial begin
+    $dumpfile("map_table_tb.vcd");
+    $dumpvars(0, map_table_tb);
+end
+
+endmodule

test/rob_test.sv

@@ -0,0 +1,115 @@
+`include "verilog/sys_defs.svh"
+// test ROB_SZ = 4 
+module rob_test;
+
+   // TAG : valid, phys_reg, ready
+   // DUT I/O
+	logic clock;
+	logic reset;
+	logic [$clog2(`ROB_SZ):0] counter;
+	logic [$clog2(`ROB_SZ)-1:0] head_idx;
+	logic [$clog2(`ROB_SZ)-1:0] tail_idx;
+	//logic [$clog2(`ROB_SZ):0] next_counter;
+	ID_ROB_PACKET id_rob; // t_in, t_old_in, write_en 
+	IC_ROB_PACKET ic_rob; // complete_idx, complete_en
+
+	ROB_ID_PACKET rob_id; // free_idx, free
+	ROB_IR_PACKET rob_ir; // retire_t, retire_t_old, retire_en
+
+	rob rob_dut (
+		.clock(clock), 
+		.reset(reset),
+		.counter(counter),
+		.head_idx(head_idx),
+		.tail_idx(tail_idx),
+		//.next_counter(next_counter),
+		.id_rob_packet(id_rob), 
+		.ic_rob_packet(ic_rob), 
+		.rob_id_packet(rob_id), 
+		.rob_ir_packet(rob_ir)
+	);
+
+
+
+    // CLOCK_PERIOD is defined on the commandline by the makefile
+    always begin 
+        #(`CLOCK_PERIOD/2.0);
+        clock = ~clock;
+    end
+
+   initial begin
+        // setup monitor and reset signals
+        $monitor("time: %3.0d id_rob_write_en: %b ic_rob_complete_idx: %2.0d ic_rob_complete_en: %b rob_id_free_idx: %2.0d rob_id_free: %b rob_ir_retire_en: %b counter: %d head_idx: %d tail_idx: %d\n",
+                 $time, id_rob.write_en, ic_rob.complete_idx, ic_rob.complete_en, rob_id.free_idx, rob_id.free, rob_ir.retire_en, counter, head_idx, tail_idx);
+
+        clock = 1'b0;
+	@(posedge clock)
+        reset = 1'b1;
+	@(posedge clock)
+	reset = 1'b0;
+	@(posedge clock)
+	/*first index*/
+	// id_rob 
+	id_rob.write_en = 1'b1;
+	ic_rob.complete_idx = 2'b00;  
+	ic_rob.complete_en = 1'b0;
+
+	/*second index*/
+	@(posedge clock)
+	id_rob.write_en = 1'b1;
+	ic_rob.complete_en = 1'b0;
+
+
+	/*third index*/
+	@(posedge clock)
+	id_rob.write_en = 1'b1;
+	ic_rob.complete_en = 1'b0;
+
+	/*fourth index*/
+	@(posedge clock)
+	id_rob.write_en = 1'b1;
+	ic_rob.complete_en = 1'b0; // full now 
+
+	/*fifth index*/
+	@(posedge clock)
+	id_rob.write_en = 1'b0;
+	ic_rob.complete_en = 1'b0;
+
+	/*sixth index*/
+	@(posedge clock)
+	id_rob.write_en = 1'b0;
+	// ic_rob --> first index is complete
+	ic_rob.complete_idx = 2'b00; 
+	ic_rob.complete_en = 1'b1;
+	@(posedge clock)
+	id_rob.write_en = 1'b0;
+	ic_rob.complete_en = 1'b0;
+
+	@(posedge clock)
+	id_rob.write_en = 1'b1;
+	ic_rob.complete_idx = 2'b01;
+	ic_rob.complete_en = 1'b1; // write & retire happens at the same time 
+
+	@(posedge clock)
+	id_rob.write_en = 1'b1;
+	ic_rob.complete_idx = 2'b01;
+	ic_rob.complete_en = 1'b0;
+
+	@(posedge clock)
+	ic_rob.complete_idx = 2'b01; 
+	ic_rob.complete_en = 1'b0;
+
+	id_rob.write_en = 1'b0;
+
+	@(posedge clock)
+	ic_rob.complete_en = 1'b1;
+	id_rob.write_en = 1'b1;
+	    #60;
+    $display("\nENDING TESTBENCH: SUCCESS!");
+    $display("@@@ Passed\n");
+    $finish; // End simulation
+   end
+endmodule
+
+
+

verilog/decoder.sv

@@ -16,7 +16,7 @@ module decoder (
     output logic          rd_mem, wr_mem, cond_branch, uncond_branch,
     output logic          csr_op, // used for CSR operations, we only use this as a cheap way to get the return code out
     output logic          halt,   // non-zero on a halt
-    output logic          illegal // non-zero on an illegal instruction
+    output logic          illegal, // non-zero on an illegal instruction
 );
 
     // Note: I recommend using an IDE's code folding feature on this block