Update CDEPS external to 3f36622.

Branch ssp-fix: "anomaly_forcing now automatically set based on compset (ISSP*)." Also updates testmods accordingly.

.gitmodules

@@ -92,7 +92,7 @@ fxDONOTUSEurl = https://github.com/ESCOMP/CMEPS.git
 [submodule "cdeps"]
 path = components/cdeps
 url = https://github.com/samsrabin/CDEPS.git
-fxtag = 547506603e1f3ac302f16e70b448d74a84947341
+fxtag = 3f36622b3bd6358d324f1aca5e90009db306963e
 fxrequired = ToplevelRequired
 # Standard Fork to compare to with "git fleximod test" to ensure personal forks aren't committed
 fxDONOTUSEurl = https://github.com/ESCOMP/CDEPS.git

cime_config/testdefs/testlist_clm.xml

@@ -1989,6 +1989,7 @@
     <machines>
       <machine name="izumi" compiler="intel" category="aux_clm"/>
       <machine name="derecho" compiler="nvhpc" category="aux_clm"/>
+      <machine name="derecho" compiler="intel" category="ssp"/>
       <machine name="izumi" compiler="gnu" category="aux_clm"/>
     </machines>
     <options>
@@ -2551,6 +2552,45 @@
       <option name="comment"  >Transient production with anomaly forcing future scenario SSP5-8.5 case</option>
     </options>
   </test>
+
+    <test name="SMS_D_Ld5" grid="f09_g17" compset="ISSP126Clm50BgcCrop" testmods="clm/default">
+    <machines>
+      <machine name="derecho" compiler="intel" category="aux_clm"/>
+      <machine name="derecho" compiler="intel" category="ssp"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment"  >Transient production with anomaly forcing future scenario SSP1-2.6 case</option>
+    </options>
+  </test>
+  <test name="SMS_D_Ld5" grid="f10_f10_mg37" compset="ISSP245Clm50BgcCrop" testmods="clm/default">
+    <machines>
+      <machine name="derecho" compiler="intel" category="ssp"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment"  >Transient production with anomaly forcing future scenario SSP2-4.5 case</option>
+    </options>
+  </test>
+  <test name="SMS_D_Ld5" grid="f09_g17" compset="ISSP370Clm50BgcCrop" testmods="clm/default">
+    <machines>
+      <machine name="derecho" compiler="intel" category="ssp"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment"  >Transient production with anomaly forcing future scenario SSP3-7.0 case</option>
+    </options>
+  </test>
+  <test name="SMS_D_Ld5" grid="f09_g17" compset="ISSP585Clm50BgcCrop" testmods="clm/default">
+    <machines>
+      <machine name="derecho" compiler="intel" category="ssp"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment"  >Transient production with anomaly forcing future scenario SSP5-8.5 case</option>
+    </options>
+  </test>
+
 
   <test name="ERP_D_Ld5" grid="f10_f10_mg37" compset="I1850Clm50Bgc" testmods="clm/nlevgrnd_small">
     <machines>