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Write to codec when changing sound frequency
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ALSO: Fix disabled audio, if DSi touch mode is set for Slot-1 with SCFG
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RocketRobz committed Sep 20, 2024
1 parent ccc88d2 commit 824c743
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Showing 11 changed files with 998 additions and 15 deletions.
2 changes: 1 addition & 1 deletion booter/arm7/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ UNIVERSAL := ../../universal
TARGET := booter
BUILD := build
SOURCES := source $(UNIVERSAL)/sdmmc/arm7/source
INCLUDES := include build $(UNIVERSAL)/sdmmc/arm7/include
INCLUDES := include build $(UNIVERSAL)/arm7/include $(UNIVERSAL)/sdmmc/arm7/include

#---------------------------------------------------------------------------------
# options for code generation
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31 changes: 28 additions & 3 deletions booter/arm7/source/main.c
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@
---------------------------------------------------------------------------------*/
#include <nds.h>
#include "blocks_codec.h"

#define SD_IRQ_STATUS (*(vu32*)0x400481C)

Expand Down Expand Up @@ -80,9 +81,33 @@ int main() {
}
}

*(vu16*)0x04004700 &= ~BIT(15); // Disable sound output: Runs before sound frequency change
*(vu16*)0x04004700 |= BIT(13); // Set 48khz sound/mic frequency
*(vu16*)0x04004700 |= BIT(15); // Enable sound output
if ((REG_SNDEXTCNT & SNDEXTCNT_ENABLE) && !(REG_SNDEXTCNT & BIT(13))) {
REG_SNDEXTCNT &= ~SNDEXTCNT_ENABLE; // Disable sound output: Runs before sound frequency change

// Reconfigure clock dividers, based on the TSC2117 datasheet.
// - We disable PLL, as MCLK is always equal to the sample frequency
// times 256, which is an integer multiple.
// - We disable ADC NADC/MADC dividers, to share the DAC clock.
// This also prevents us from having to reconfigure the PLL multipliers
// for 32kHz/47kHz.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);

/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
} */

REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | SNDEXTCNT_FREQ_47KHZ | SNDEXTCNT_ENABLE;
// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
}

// clear sound registers
dmaFillWords(0, (void*)0x04000400, 0x100);
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2 changes: 1 addition & 1 deletion booter_fc/arm7/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ UNIVERSAL := ../../universal
TARGET := booter
BUILD := build
SOURCES := source $(UNIVERSAL)/sdmmc/arm7/source
INCLUDES := include build $(UNIVERSAL)/sdmmc/arm7/include
INCLUDES := include build $(UNIVERSAL)/arm7/include $(UNIVERSAL)/sdmmc/arm7/include

#---------------------------------------------------------------------------------
# options for code generation
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99 changes: 96 additions & 3 deletions booter_fc/arm7/source/main.c
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,11 @@
---------------------------------------------------------------------------------*/
#include <nds.h>
#include "blocks_codec.h"

void my_installSystemFIFO(void);
u8 my_cdcReadReg(u8 bank, u8 reg);
void my_cdcWriteReg(u8 bank, u8 reg, u8 value);

//---------------------------------------------------------------------------------
void ReturntoDSiMenu() {
Expand Down Expand Up @@ -64,6 +67,70 @@ void powerButtonCB() {
exitflag = true;
}

static void DSiTouchscreenMode(void) {
if (my_cdcReadReg(CDC_SOUND, 0x22) != 0xF0) return;

// Touchscreen
my_cdcWriteReg(0, 0x01, 0x01);
my_cdcWriteReg(0, 0x39, 0x66);
my_cdcWriteReg(1, 0x20, 0x16);
my_cdcWriteReg(0, 0x04, 0x00);
my_cdcWriteReg(0, 0x12, 0x81);
my_cdcWriteReg(0, 0x13, 0x82);
my_cdcWriteReg(0, 0x51, 0x82);
my_cdcWriteReg(0, 0x51, 0x00);
my_cdcWriteReg(0, 0x04, 0x03);
my_cdcWriteReg(0, 0x05, 0xA1);
my_cdcWriteReg(0, 0x06, 0x15);
my_cdcWriteReg(0, 0x0B, 0x87);
my_cdcWriteReg(0, 0x0C, 0x83);
my_cdcWriteReg(0, 0x12, 0x87);
my_cdcWriteReg(0, 0x13, 0x83);
my_cdcWriteReg(3, 0x10, 0x88);
my_cdcWriteReg(4, 0x08, 0x7F);
my_cdcWriteReg(4, 0x09, 0xE1);
my_cdcWriteReg(4, 0x0A, 0x80);
my_cdcWriteReg(4, 0x0B, 0x1F);
my_cdcWriteReg(4, 0x0C, 0x7F);
my_cdcWriteReg(4, 0x0D, 0xC1);
my_cdcWriteReg(0, 0x41, 0x08);
my_cdcWriteReg(0, 0x42, 0x08);
my_cdcWriteReg(0, 0x3A, 0x00);
my_cdcWriteReg(4, 0x08, 0x7F);
my_cdcWriteReg(4, 0x09, 0xE1);
my_cdcWriteReg(4, 0x0A, 0x80);
my_cdcWriteReg(4, 0x0B, 0x1F);
my_cdcWriteReg(4, 0x0C, 0x7F);
my_cdcWriteReg(4, 0x0D, 0xC1);
my_cdcWriteReg(1, 0x2F, 0x2B);
my_cdcWriteReg(1, 0x30, 0x40);
my_cdcWriteReg(1, 0x31, 0x40);
my_cdcWriteReg(1, 0x32, 0x60);
my_cdcWriteReg(0, 0x74, 0x82);
my_cdcWriteReg(0, 0x74, 0x92);
my_cdcWriteReg(0, 0x74, 0xD2);
my_cdcWriteReg(1, 0x21, 0x20);
my_cdcWriteReg(1, 0x22, 0xF0);
my_cdcWriteReg(0, 0x3F, 0xD4);
my_cdcWriteReg(1, 0x23, 0x44);
my_cdcWriteReg(1, 0x1F, 0xD4);
my_cdcWriteReg(1, 0x28, 0x4E);
my_cdcWriteReg(1, 0x29, 0x4E);
my_cdcWriteReg(1, 0x24, 0x9E);
my_cdcWriteReg(1, 0x25, 0x9E);
my_cdcWriteReg(1, 0x20, 0xD4);
my_cdcWriteReg(1, 0x2A, 0x14);
my_cdcWriteReg(1, 0x2B, 0x14);
my_cdcWriteReg(1, 0x26, 0xA7);
my_cdcWriteReg(1, 0x27, 0xA7);
my_cdcWriteReg(0, 0x40, 0x00);
my_cdcWriteReg(0, 0x3A, 0x60);

// Finish up!
my_cdcReadReg (CDC_TOUCHCNT, 0x02);
my_cdcWriteReg(CDC_TOUCHCNT, 0x02, 0x00);
}

//---------------------------------------------------------------------------------
int main() {
//---------------------------------------------------------------------------------
Expand All @@ -74,9 +141,35 @@ int main() {
*(vu16*)(0x04004014) = 0x264C;
*(vu16*)(0x04004C02) = 0x4000; // enable powerbutton irq (Fix for Unlaunch 1.3)

*(vu16*)0x04004700 &= ~BIT(15); // Disable sound output: Runs before sound frequency change
*(vu16*)0x04004700 |= BIT(13); // Set 48khz sound/mic frequency (DSi/3DS only)
*(vu16*)0x04004700 |= BIT(15); // Enable sound output
DSiTouchscreenMode(); // Fix disabled audio, if DSi touch mode is set

if ((REG_SNDEXTCNT & SNDEXTCNT_ENABLE) && !(REG_SNDEXTCNT & BIT(13))) {
REG_SNDEXTCNT &= ~SNDEXTCNT_ENABLE; // Disable sound output: Runs before sound frequency change

// Reconfigure clock dividers, based on the TSC2117 datasheet.
// - We disable PLL, as MCLK is always equal to the sample frequency
// times 256, which is an integer multiple.
// - We disable ADC NADC/MADC dividers, to share the DAC clock.
// This also prevents us from having to reconfigure the PLL multipliers
// for 32kHz/47kHz.
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);

/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
} */

REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | SNDEXTCNT_FREQ_47KHZ | SNDEXTCNT_ENABLE;
// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
}

// clear sound registers
dmaFillWords(0, (void*)0x04000400, 0x100);
Expand Down
212 changes: 212 additions & 0 deletions booter_fc/arm7/source/my_codec.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,212 @@
/*---------------------------------------------------------------------------------
DSi "codec" Touchscreen/Sound Controller control for ARM7
Copyright (C) 2017
fincs
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any
damages arising from the use of this software.
Permission is granted to anyone to use this software for any
purpose, including commercial applications, and to alter it and
redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you
must not claim that you wrote the original software. If you use
this software in a product, an acknowledgment in the product
documentation would be appreciated but is not required.
2. Altered source versions must be plainly marked as such, and
must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source
distribution.
---------------------------------------------------------------------------------*/

#include "my_codec.h"

//---------------------------------------------------------------------------------
static u8 my_readTSC(u8 reg) {
//---------------------------------------------------------------------------------

while (REG_SPICNT & 0x80);

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH | SPI_CONTINUOUS;
REG_SPIDATA = 1 | (reg << 1);

while (REG_SPICNT & 0x80);

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH;
REG_SPIDATA = 0;

while (REG_SPICNT & 0x80);
return REG_SPIDATA;
}

//---------------------------------------------------------------------------------
static void my_writeTSC(u8 reg, u8 value) {
//---------------------------------------------------------------------------------

while (REG_SPICNT & 0x80);

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH | SPI_CONTINUOUS;
REG_SPIDATA = reg << 1;

while (REG_SPICNT & 0x80);

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH;
REG_SPIDATA = value;
}

//---------------------------------------------------------------------------------
static void my_bankSwitchTSC(u8 bank) {
//---------------------------------------------------------------------------------

static u8 curBank = 0x63;
if (bank != curBank) {
my_writeTSC(curBank == 0xFF ? 0x7F : 0x00, bank);
curBank = bank;
}
}

//---------------------------------------------------------------------------------
u8 my_cdcReadReg(u8 bank, u8 reg) {
//---------------------------------------------------------------------------------

my_bankSwitchTSC(bank);
return my_readTSC(reg);
}

//---------------------------------------------------------------------------------
void my_cdcReadRegArray(u8 bank, u8 reg, void* data, u8 size) {
//---------------------------------------------------------------------------------

u8* out = (u8*)data;
my_bankSwitchTSC(bank);

while (REG_SPICNT & 0x80);

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH | SPI_CONTINUOUS;
REG_SPIDATA = 1 | (reg << 1);

while (REG_SPICNT & 0x80);

for (; size > 1; size--) {
REG_SPIDATA = 0;
while (REG_SPICNT & 0x80);
*out++ = REG_SPIDATA;
}

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH;
REG_SPIDATA = 0;

while (REG_SPICNT & 0x80);

*out++ = REG_SPIDATA;
}

//---------------------------------------------------------------------------------
void my_cdcWriteReg(u8 bank, u8 reg, u8 value) {
//---------------------------------------------------------------------------------

my_bankSwitchTSC(bank);
my_writeTSC(reg, value);
}

//---------------------------------------------------------------------------------
void my_cdcWriteRegMask(u8 bank, u8 reg, u8 mask, u8 value) {
//---------------------------------------------------------------------------------

my_bankSwitchTSC(bank);
my_writeTSC(reg, (my_readTSC(reg) &~ mask) | (value & mask));
}

//---------------------------------------------------------------------------------
void my_cdcWriteRegArray(u8 bank, u8 reg, const void* data, u8 size) {
//---------------------------------------------------------------------------------

const u8* in = (u8*)data;
my_bankSwitchTSC(bank);

while (REG_SPICNT & 0x80);

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH | SPI_CONTINUOUS;
REG_SPIDATA = reg << 1;

while (REG_SPICNT & 0x80);

for (; size > 1; size--) {
REG_SPIDATA = *in++;
while (REG_SPICNT & 0x80);
}

REG_SPICNT = SPI_ENABLE | SPI_BAUD_4MHz | SPI_DEVICE_TOUCH;
REG_SPIDATA = *in++;
}

//---------------------------------------------------------------------------------
void my_cdcTouchInit(void) {
//---------------------------------------------------------------------------------

my_cdcWriteRegMask(CDC_TOUCHCNT, 0x0E, 0x80, 0<<7);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x02, 0x18, 3<<3);
my_cdcWriteReg (CDC_TOUCHCNT, 0x0F, 0xA0);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x0E, 0x38, 5<<3);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x0E, 0x40, 0<<6);
my_cdcWriteReg (CDC_TOUCHCNT, 0x03, 0x8B);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x05, 0x07, 4<<0);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x04, 0x07, 6<<0);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x04, 0x70, 4<<4);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x12, 0x07, 0<<0);
my_cdcWriteRegMask(CDC_TOUCHCNT, 0x0E, 0x80, 1<<7);
}

//---------------------------------------------------------------------------------
bool my_cdcTouchPenDown(void) {
//---------------------------------------------------------------------------------

return (my_cdcReadReg(CDC_TOUCHCNT, 0x09) & 0xC0) != 0x40 && !(my_cdcReadReg(CDC_TOUCHCNT, 0x0E) & 0x02);
}

//---------------------------------------------------------------------------------
bool my_cdcTouchRead(touchPosition* pos) {
//---------------------------------------------------------------------------------

u8 raw[4*2*5];
u16 arrayX[5], arrayY[5], arrayZ1[5], arrayZ2[5];
u32 sumX, sumY, sumZ1, sumZ2;
int i;

my_cdcReadRegArray(CDC_TOUCHDATA, 0x01, raw, sizeof(raw));

for (i = 0; i < 5; i ++) {
arrayX[i] = (raw[i*2+ 0]<<8) | raw[i*2+ 1];
arrayY[i] = (raw[i*2+10]<<8) | raw[i*2+11];
arrayZ1[i] = (raw[i*2+20]<<8) | raw[i*2+21];
arrayZ2[i] = (raw[i*2+30]<<8) | raw[i*2+31];
if ((arrayX[i] & 0xF000) || (arrayY[i] & 0xF000)) {
pos->rawx = 0;
pos->rawy = 0;
return false;
}
}

// TODO: For now we just average all values without removing inaccurate values
sumX = 0;
sumY = 0;
sumZ1 = 0;
sumZ2 = 0;
for (i = 0; i < 5; i ++) {
sumX += arrayX[i];
sumY += arrayY[i];
sumZ1 += arrayZ1[i];
sumZ2 += arrayZ2[i];
}

pos->rawx = sumX / 5;
pos->rawy = sumY / 5;
pos->z1 = sumZ1 / 5;
pos->z2 = sumZ2 / 5;
return true;
}
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