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Fix low quality sound output when switching frequency to 48khz
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@RocketRobz
RocketRobz committed Sep 21, 2024
1 parent 8aef783 commit 679fd28
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Showing 4 changed files with 25 additions and 23 deletions.
14 changes: 7 additions & 7 deletions booter/arm7/source/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -90,20 +90,20 @@ int main() {
// - We disable ADC NADC/MADC dividers, to share the DAC clock.
// This also prevents us from having to reconfigure the PLL multipliers
// for 32kHz/47kHz.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
// This produces low quality output
/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK); */

/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);

// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
} */
// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));

REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | SNDEXTCNT_FREQ_47KHZ | SNDEXTCNT_ENABLE;
// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
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16 changes: 8 additions & 8 deletions booter_fc/arm7/source/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -152,20 +152,20 @@ int main() {
// - We disable ADC NADC/MADC dividers, to share the DAC clock.
// This also prevents us from having to reconfigure the PLL multipliers
// for 32kHz/47kHz.
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
// This produces low quality output
/* my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK); */

/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);

// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
} */
// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));

REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | SNDEXTCNT_FREQ_47KHZ | SNDEXTCNT_ENABLE;
// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
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9 changes: 5 additions & 4 deletions slot1launch/bootloader/source/main.arm7.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1027,15 +1027,16 @@ void arm7_main (void) {
// - We disable ADC NADC/MADC dividers, to share the DAC clock.
// This also prevents us from having to reconfigure the PLL multipliers
// for 32kHz/47kHz.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
// This produces low quality output
/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE); */

if (soundFreq)
{
Expand All @@ -1048,7 +1049,7 @@ void arm7_main (void) {
// Configure a PLL multiplier/divider of 21/2, and a NDAC/NADC divider of 7.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(7));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 21);
} */
}

REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | (soundFreq ? SNDEXTCNT_FREQ_47KHZ : SNDEXTCNT_FREQ_32KHZ) | SNDEXTCNT_ENABLE;
// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
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9 changes: 5 additions & 4 deletions slot1launch/bootloaderAlt/source/main.arm7.c
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Original file line number Diff line number Diff line change
Expand Up @@ -734,15 +734,16 @@ void arm7_main (void) {
// - We disable ADC NADC/MADC dividers, to share the DAC clock.
// This also prevents us from having to reconfigure the PLL multipliers
// for 32kHz/47kHz.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
// This produces low quality output
/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE); */

if (soundFreq)
{
Expand All @@ -755,7 +756,7 @@ void arm7_main (void) {
// Configure a PLL multiplier/divider of 21/2, and a NDAC/NADC divider of 7.
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(7));
cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 21);
} */
}

REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | (soundFreq ? SNDEXTCNT_FREQ_47KHZ : SNDEXTCNT_FREQ_32KHZ) | SNDEXTCNT_ENABLE;
// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
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