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# uccp420wlan | ||
This is a SoftMAC (mac80211) based WiFi driver for Imagination's Explorer RPU uccp420. | ||
This supports Dual Band WiFi with 2.4GHz - 2x2 b/g/n 40MHz, 5GHz - 2x2 a/n/11ac 80MHz modes. | ||
This is a SoftMAC (mac80211) based WiFi driver for Imagination's Explorer RPU Series 4 (uccp420). | ||
This driver supports | ||
- Dual Band 2x2 MIMO WiFi with 2.4GHz - b/g/n 40MHz, 5GHz - a/n/ac 80MHz modes. | ||
- STA, SoftAP, P2P-GC/GO and IBSS modes | ||
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/* | ||
* File Name : hal_hostport.h | ||
* | ||
* This file contains the definitions specific to HOSPORT comms | ||
* | ||
* Copyright (c) 2011, 2012, 2013, 2014 Imagination Technologies Ltd. | ||
* All rights reserved | ||
* | ||
* This program is free software; you can redistribute it and/or | ||
* modify it under the terms of the GNU General Public License | ||
* as published by the Free Software Foundation; either version 2 | ||
* of the License, or (at your option) any later version. | ||
* | ||
* This program is distributed in the hope that it will be useful, | ||
* but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
* GNU General Public License for more details. | ||
* | ||
* You should have received a copy of the GNU General Public License | ||
* along with this program; if not, write to the Free Software | ||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, | ||
* USA. | ||
*/ | ||
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#ifndef _UCCP420WLAN_HAL_HOSTPORT_H_ | ||
#define _UCCP420WLAN_HAL_HOSTPORT_H_ | ||
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#include <linux/interrupt.h> | ||
#include <linux/skbuff.h> | ||
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#include <hal.h> | ||
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#if defined(__cplusplus) | ||
extern "C" | ||
{ | ||
#endif /* __cplusplus */ | ||
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struct hal_priv { | ||
/* UCCP Host RAM mappings*/ | ||
void __iomem *base_addr_uccp_host_ram; | ||
void __iomem *tx_base_addr_uccp_host_ram; | ||
void __iomem *rx_base_addr_uccp_host_ram; | ||
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/* UCCP and GRAM mappings */ | ||
unsigned long uccp_mem_addr; | ||
unsigned long gram_mem_addr; | ||
unsigned long uccp_sysbus_base_addr; | ||
unsigned long uccp_perip_base_addr; | ||
unsigned long gram_base_addr; | ||
unsigned long shm_offset; | ||
unsigned long hal_disabled; | ||
unsigned long gram_b4_addr; | ||
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/* DTS entries */ | ||
unsigned long uccp_sysbus_base; | ||
unsigned long uccp_sysbus_len; | ||
unsigned long uccp_perip_base; | ||
unsigned long uccp_perip_len; | ||
unsigned long uccp_pkd_gram_base; | ||
unsigned long uccp_pkd_gram_len; | ||
unsigned long uccp_gram_base; | ||
unsigned long uccp_gram_len; | ||
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/* TX */ | ||
struct sk_buff_head txq; | ||
struct tasklet_struct tx_tasklet; | ||
unsigned short cmd_cnt; | ||
struct buf_info *tx_buf_info; | ||
struct hal_tx_data *hal_tx_data; | ||
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/* RX */ | ||
struct sk_buff_head rxq; | ||
struct tasklet_struct rx_tasklet; | ||
struct tasklet_struct recv_tasklet; | ||
unsigned short event_cnt; | ||
msg_handler rcv_handler; | ||
struct buf_info *rx_buf_info; | ||
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/* Buffers info from IF layer*/ | ||
unsigned int tx_bufs; | ||
unsigned int rx_bufs_2k; | ||
unsigned int rx_bufs_12k; | ||
unsigned int max_data_size; | ||
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/* Temp storage to refill first and process next*/ | ||
struct sk_buff_head refillq; | ||
int irq; | ||
}; | ||
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#if defined(__cplusplus) | ||
} | ||
#endif /* __cplusplus */ | ||
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#endif /* _UCCP420WLAN_HAL_HOSTPORT_H_ */ | ||
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/* EOF */ |
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/* RPU Porting information: Based on RPU Config. | ||
* These are the only values which need to be modified as per | ||
* a) host memory map | ||
* b) HOSt <->MCU interrupt configuration. | ||
* c) RPU Config specific details | ||
*/ | ||
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/********************************************************************* | ||
* RPU Config Specific Details | ||
********************************************************************* | ||
*/ | ||
#define HAL_UCCP_GRAM_BASE 0xB7000000 | ||
#define HAL_UCCP_GRAM_LEN 0x1eac0 | ||
#define HAL_SHARED_MEM_OFFSET 0x45ffc | ||
/* fwldr.c converts these to HOST addresses | ||
* so pass RPU addresses here. | ||
* From: uccrunTime/Platform/configs | ||
*/ | ||
#define UCCP_COREA_REGION_START 0x80880000 | ||
#define UCCP_COREA_REGION_LEN 0x4C000 | ||
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#define UCCP_COREB_REGION_START 0x82000000 | ||
#define UCCP_COREB_REGION_LEN 0x4C000 | ||
/********************************************************************* | ||
*/ | ||
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/******************************************************************** | ||
* HOST processor to Meta Processor on RPU Communications Registers | ||
******************************************************************** | ||
* Refer: Volt UCCP.Technical Reference Manual.pdf | ||
* The host_to_mtx_cmd register is written to by the host in order to | ||
* send data to the META. The act of writing causes an event on the META | ||
* (the host_int interrupt occurs). The META handles this event by reading | ||
* host_to_mtx_cmd, collecting the message data. | ||
* | ||
* The META clears the interrupt and in the process acknowledges reception | ||
* of the message by writing to the mtx_to_host_ack register. The host checks | ||
* for this acknowledgement by reading host_to_mtx_cmd, checking the state of | ||
* the HOST_INT bit. | ||
* | ||
* A message initiated by the META and destined for the host uses the same | ||
* scheme, but utilising the mtx_to_host_cmd and host_to_mtx_ack registers and | ||
* by responding to the mtx_int interrupt. | ||
*/ | ||
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/* SYSBUS - System Control - REGSYSREG | ||
* UCCP_CORE_REG is a subset of System Bus Registers | ||
*/ | ||
#define HAL_UCCP_CORE_REG_OFFSET 0x400 | ||
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/* Register HOST_TO_MTX_CMD */ | ||
#define HOST_TO_MTX_CMD 0x0030 | ||
#define HOST_TO_MTX_CMD_ADDR ((hpriv->uccp_mem_addr) + \ | ||
HOST_TO_MTX_CMD) | ||
#define MTX_HOST_INT_SHIFT 31 | ||
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/* Register MTX_TO_HOST_CMD */ | ||
#define MTX_TO_HOST_CMD 0x0034 | ||
#define MTX_TO_HOST_CMD_ADDR ((hpriv->uccp_mem_addr) + \ | ||
MTX_TO_HOST_CMD) | ||
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/* Register HOST_TO_MTX_ACK */ | ||
#define HOST_TO_MTX_ACK 0x0038 | ||
#define HOST_TO_MTX_ACK_ADDR ((hpriv->uccp_mem_addr) + \ | ||
HOST_TO_MTX_ACK) | ||
#define MTX_INT_CLR_SHIFT 31 | ||
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/* Register MTX_TO_HOST_ACK */ | ||
#define MTX_TO_HOST_ACK 0x003C | ||
#define MTX_TO_HOST_ACK_ADDR ((hpriv->uccp_mem_addr) + \ | ||
MTX_TO_HOST_ACK) | ||
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/* Register MTX_INT_ENABLE | ||
* Enable INT line within META Block | ||
*/ | ||
#define MTX_INT_ENABLE 0x0044 | ||
#define MTX_INT_ENABLE_ADDR ((hpriv->uccp_mem_addr) + \ | ||
MTX_INT_ENABLE) | ||
#define MTX_INT_EN_SHIFT 31 | ||
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/* System Level Interrupt Control for each block. | ||
* Enable INT line for META block. | ||
*/ | ||
#define SYS_INT_ENAB 0x0000 | ||
#define SYS_INT_ENAB_ADDR ((hpriv->uccp_mem_addr) + SYS_INT_ENAB) | ||
#define SYS_INT_MTX_IRQ_ENAB_SHIFT 15 | ||
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/********************************************************************* | ||
*/ |
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