Merge pull request #15 from francois-berder-imgtec/rel

Merge dev to rel branch

README.md

@@ -1,4 +1,6 @@
 # uccp420wlan
-This is a SoftMAC (mac80211) based WiFi driver for Imagination's Explorer RPU uccp420.
-This supports Dual Band WiFi with 2.4GHz - 2x2 b/g/n 40MHz, 5GHz - 2x2 a/n/11ac 80MHz modes.
+This is a SoftMAC (mac80211) based WiFi driver for Imagination's Explorer RPU Series 4 (uccp420).
+This driver supports 
+      - Dual Band 2x2 MIMO WiFi with 2.4GHz - b/g/n 40MHz, 5GHz - a/n/ac 80MHz modes.
+      - STA, SoftAP, P2P-GC/GO and IBSS modes
 

inc/core.h

@@ -143,7 +143,7 @@ extern spinlock_t tsf_lock;
 #define CH_PROG_TIMEOUT 500   /* In milli-seconds*/
 #define CH_PROG_TIMEOUT_TICKS msecs_to_jiffies(CH_PROG_TIMEOUT)
 
-#define QUEUE_FLUSH_TIMEOUT  2000   /* Specify delay in milli-seconds*/
+#define QUEUE_FLUSH_TIMEOUT  5000   /* Specify delay in milli-seconds*/
 #define QUEUE_FLUSH_TIMEOUT_TICKS   msecs_to_jiffies(QUEUE_FLUSH_TIMEOUT)
 
 #define TX_DEINIT_TIMEOUT 5000
@@ -498,6 +498,7 @@ struct wifi_stats {
 						   * RX circular buffers
 						   */
 	unsigned int rx_mic_fail_cnt; /* Num of MIC failures */
+	unsigned int deagg_bufOverFlow_cnt; /* RX buffer overflow count */
 
 	/* HAL related */
 	unsigned int hal_cmd_cnt; /* Num of commands received by HAL from the
@@ -507,6 +508,7 @@ struct wifi_stats {
 	unsigned int hal_ext_ptr_null_cnt; /* Num of packets dropped due to lack
 					    * of Ext Ram buffers from host
 					    */
+	unsigned int hal_int_ptr_null_cnt;
 
 	/*RF Calibration Data*/
 	unsigned int rf_calib_data_length;
@@ -826,6 +828,8 @@ __s32 __attribute__((weak)) frc_to_atu(__u32 frccnt, __u64 *patu, s32 dir);
 int __attribute__((weak)) get_evt_timer_freq(unsigned int *mask,
 						unsigned int *num,
 						unsigned int *denom);
+int __attribute__((weak)) atu_get_cur_timestamps(unsigned long long *t,
+						 unsigned int *ts);
 
 int tx_queue_map(int queue);
 int tx_queue_unmap(int queue);

inc/hal.h

@@ -25,13 +25,113 @@
 #ifndef _UCCP420WLAN_HAL_H_
 #define _UCCP420WLAN_HAL_H_
 
+#define _PACKED_  __attribute__((__packed__))
+
 #define HOST_MOD_ID 0
 #define UMAC_MOD_ID 1
 #define LMAC_MOD_ID 2
 #define MODULE_MAX 3
 
+#define MAX_RX_BUF_PTR_PER_CMD (16)
+#define MAX_DATA_SIZE_12K (12 * 1024)
+#define MAX_DATA_SIZE_8K (8 * 1024)
+#define MAX_DATA_SIZE_2K (2 * 1024)
+
+#define NUM_TX_DESC 12
+#define NUM_FRAMES_IN_TX_DESC 32
+#define NUM_BYTES_PER_FRAME 9
+#define TX_DESC_HAL_SIZE (NUM_FRAMES_IN_TX_DESC * NUM_BYTES_PER_FRAME)
+
 #define HAL_PRIV_DATA_SIZE 8
 
+#define HAL_HOST_ZONE_DMA_LEN (64 * 1024 * 1024)
+#define HAL_SHARED_MEM_MAX_MSG_SIZE 60
+#define HAL_SHARED_MEM_MAX_TX_SIZE 0xD80
+
+/* Command, Event, Tx Data and Buff mappping offsets */
+#define HAL_COMMAND_OFFSET (0)
+#define HAL_EVENT_OFFSET (HAL_COMMAND_OFFSET + HAL_SHARED_MEM_MAX_MSG_SIZE)
+#define HAL_TX_DATA_OFFSET (HAL_EVENT_OFFSET   + HAL_SHARED_MEM_MAX_MSG_SIZE)
+#define HAL_AXD_DATA_OFFSET (HAL_TX_DATA_OFFSET + HAL_SHARED_MEM_MAX_TX_SIZE)
+
+#define HAL_GRAM_CMD_START ((hpriv->gram_mem_addr) + HAL_COMMAND_OFFSET)
+#define HAL_GRAM_EVENT_START ((hpriv->gram_mem_addr) + HAL_EVENT_OFFSET)
+#define HAL_GRAM_TX_DATA_START ((hpriv->gram_mem_addr) + HAL_TX_DATA_OFFSET)
+#define HAL_AXD_DATA_START ((hpriv->gram_mem_addr) + HAL_AXD_DATA_OFFSET)
+
+#define HAL_GRAM_CMD_LEN (HAL_GRAM_CMD_START + 8)
+#define HAL_GRAM_TX_DATA_LEN (HAL_GRAM_TX_DATA_START + 0)
+#define HAL_GRAM_TX_DATA_OFFSET	(HAL_GRAM_TX_DATA_START + 3)
+#define HAL_GRAM_TX_DATA_ADDR (HAL_GRAM_TX_DATA_START + 6)
+
+#define HAL_HOST_BOUNCE_BUF_LEN (4 * 1024 * 1024)
+#define HAL_HOST_NON_BOUNCE_BUF_LEN (60 * 1024 * 1024)
+
+/*RPU DUMP Regions and Commands*/
+#define UCCP_REGION_TYPE_COREA 0
+#define UCCP_REGION_TYPE_COREB 1
+
+enum hal_rpu_testmode_cmd {
+	HAL_RPU_TM_CMD_ALL	= 0,
+	HAL_RPU_TM_CMD_GRAM	= 1,
+	HAL_RPU_TM_CMD_COREA	= 2,
+	HAL_RPU_TM_CMD_COREB	= 3,
+	HAL_RPU_TM_CMD_PERIP	= 4,
+	HAL_RPU_TM_CMD_SYSBUS	= 5,
+};
+
+struct buf_info {
+	dma_addr_t dma_buf;
+	void __iomem *src_ptr;
+	unsigned int dma_buf_len;
+	unsigned int dma_buf_priv;   /* Is the DMA buffer in our private area */
+	struct sk_buff *skb;
+} _PACKED_;
+
+struct hal_tx_data {
+	unsigned int data_len:24;
+	unsigned long address:24;
+	unsigned long offset:24;
+} _PACKED_;
+
+struct hal_hdr {
+	/*! 0xffffffff - hal command or hal event
+	 *  0x0 - lmac command or lmac event
+	 */
+	unsigned int id;
+	/*! Data pointer of commands with payload
+	 *  this field is valid only if descriptor id
+	 *  of command header is set to some value
+	 *  other.
+	 */
+	unsigned int data_ptr;
+} _PACKED_;
+
+struct hal_rx_pkt_info {
+	/* Rx descriptor */
+	unsigned int desc;
+	unsigned int ptr;
+} _PACKED_;
+
+struct hal_rx_command {
+	unsigned int rx_pkt_cnt;
+	struct hal_rx_pkt_info rx_pkt[MAX_RX_BUF_PTR_PER_CMD];
+} _PACKED_;
+
+struct cmd_hal {
+	struct hal_hdr hdr;
+	struct hal_rx_command rx_pkt_data;
+} _PACKED_;
+
+struct event_hal {
+	struct hal_hdr hdr;
+	unsigned int rx_pkt_cnt;
+	unsigned int rx_pkt_desc[16];
+} _PACKED_;
+
+int _uccp420wlan_80211if_init(struct proc_dir_entry **);
+void _uccp420wlan_80211if_exit(void);
+int reset_hal_params(void);
 typedef int (*msg_handler)(void *, unsigned char);
 
 struct hal_ops_tag {
@@ -59,6 +159,8 @@ struct hal_ops_tag {
 	int (*get_dump_perip)(unsigned long *dump_start);
 	int (*get_dump_sysbus)(unsigned long *dump_start);
 	int (*get_dump_len)(unsigned long);
+	int (*update_axd_timestamps)(void);
+	unsigned int (*get_axd_buf_phy_addr)(void);
 };
 
 extern struct hal_ops_tag hal_ops;

inc/hal_hostport.h

@@ -0,0 +1,97 @@
+/*
+ * File Name  : hal_hostport.h
+ *
+ * This file contains the definitions specific to HOSPORT comms
+ *
+ * Copyright (c) 2011, 2012, 2013, 2014 Imagination Technologies Ltd.
+ * All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
+ * USA.
+ */
+
+#ifndef _UCCP420WLAN_HAL_HOSTPORT_H_
+#define _UCCP420WLAN_HAL_HOSTPORT_H_
+
+#include <linux/interrupt.h>
+#include <linux/skbuff.h>
+
+#include <hal.h>
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif /* __cplusplus */
+
+struct hal_priv {
+	/* UCCP Host RAM mappings*/
+	void __iomem *base_addr_uccp_host_ram;
+	void __iomem *tx_base_addr_uccp_host_ram;
+	void __iomem *rx_base_addr_uccp_host_ram;
+
+	/* UCCP and GRAM mappings */
+	unsigned long uccp_mem_addr;
+	unsigned long gram_mem_addr;
+	unsigned long uccp_sysbus_base_addr;
+	unsigned long uccp_perip_base_addr;
+	unsigned long gram_base_addr;
+	unsigned long shm_offset;
+	unsigned long hal_disabled;
+	unsigned long gram_b4_addr;
+
+	/* DTS entries */
+	unsigned long uccp_sysbus_base;
+	unsigned long uccp_sysbus_len;
+	unsigned long uccp_perip_base;
+	unsigned long uccp_perip_len;
+	unsigned long uccp_pkd_gram_base;
+	unsigned long uccp_pkd_gram_len;
+	unsigned long uccp_gram_base;
+	unsigned long uccp_gram_len;
+
+	/* TX */
+	struct sk_buff_head txq;
+	struct tasklet_struct tx_tasklet;
+	unsigned short cmd_cnt;
+	struct buf_info *tx_buf_info;
+	struct hal_tx_data *hal_tx_data;
+
+	/* RX */
+	struct sk_buff_head rxq;
+	struct tasklet_struct rx_tasklet;
+	struct tasklet_struct recv_tasklet;
+	unsigned short event_cnt;
+	msg_handler rcv_handler;
+	struct buf_info *rx_buf_info;
+
+	/* Buffers info from IF layer*/
+	unsigned int tx_bufs;
+	unsigned int rx_bufs_2k;
+	unsigned int rx_bufs_12k;
+	unsigned int max_data_size;
+
+	/* Temp storage to refill first and process next*/
+	struct sk_buff_head refillq;
+	int irq;
+};
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _UCCP420WLAN_HAL_HOSTPORT_H_ */
+
+/* EOF */

inc/host_umac_if.h

@@ -72,6 +72,11 @@
 
 #define RF_PARAMS_SIZE	369
 #define MAX_RF_CALIB_DATA 900
+
+/* AXD */
+#define STREAM_SYNC_MAGIC_NUM 0xCCCCFFFF
+#define AXD_BUF_ADDR 0x3f8000
+
 struct hal_data {
 	unsigned char hal_data[HAL_PRIV_DATA_SIZE];
 } __packed;
@@ -265,6 +270,7 @@ struct umac_event_mac_stats {
 	unsigned int roc_stop;
 	unsigned int roc_complete;
 	unsigned int roc_stop_complete;
+	unsigned int deagg_bufOverFlow_cnt;
 	/* TX related */
 	unsigned int tx_cmd_cnt; /* Num of TX commands received from host */
 	unsigned int tx_done_cnt; /* Num of Tx done events sent to host */
@@ -306,6 +312,9 @@ struct umac_event_mac_stats {
 	unsigned int hal_ext_ptr_null_cnt; /* Num of packets dropped due to lack
 					    * of Ext Ram buffers from host
 					    */
+	unsigned int hal_int_ptr_null_cnt; /* Num of packets droped due to lack
+					    * of internal hal event buffers
+					    */
 
 } __packed;
 

inc/rpu.h

@@ -0,0 +1,89 @@
+/* RPU Porting information: Based on RPU Config.
+ * These are the only values which need to be modified as per
+ * a) host memory map
+ * b) HOSt <->MCU interrupt configuration.
+ * c) RPU Config specific details
+ */
+
+/*********************************************************************
+ * RPU Config Specific Details
+ *********************************************************************
+ */
+#define HAL_UCCP_GRAM_BASE 0xB7000000
+#define HAL_UCCP_GRAM_LEN 0x1eac0
+#define HAL_SHARED_MEM_OFFSET 0x45ffc
+/* fwldr.c converts these to HOST addresses
+ * so pass RPU addresses here.
+ * From: uccrunTime/Platform/configs
+ */
+#define UCCP_COREA_REGION_START 0x80880000
+#define UCCP_COREA_REGION_LEN 0x4C000
+
+#define UCCP_COREB_REGION_START 0x82000000
+#define UCCP_COREB_REGION_LEN 0x4C000
+/*********************************************************************
+ */
+
+/********************************************************************
+ * HOST processor to Meta Processor on RPU Communications Registers
+ ********************************************************************
+ * Refer: Volt UCCP.Technical Reference Manual.pdf
+ * The host_to_mtx_cmd register is written to by the host in order to
+ * send data to the META. The act of writing causes an event on the META
+ * (the host_int interrupt occurs). The META handles this event by reading
+ * host_to_mtx_cmd, collecting the message data.
+ *
+ * The META clears the interrupt and in the process acknowledges reception
+ * of the message by writing to the mtx_to_host_ack register. The host checks
+ * for this acknowledgement by reading host_to_mtx_cmd, checking the state of
+ * the HOST_INT bit.
+ *
+ * A message initiated by the META and destined for the host uses the same
+ * scheme, but utilising the mtx_to_host_cmd and host_to_mtx_ack registers and
+ * by responding to the mtx_int interrupt.
+ */
+
+/* SYSBUS - System Control - REGSYSREG
+ * UCCP_CORE_REG is a subset of System Bus Registers
+ */
+#define HAL_UCCP_CORE_REG_OFFSET	0x400
+
+/* Register HOST_TO_MTX_CMD */
+#define HOST_TO_MTX_CMD 0x0030
+#define HOST_TO_MTX_CMD_ADDR ((hpriv->uccp_mem_addr) + \
+				    HOST_TO_MTX_CMD)
+#define MTX_HOST_INT_SHIFT 31
+
+/* Register MTX_TO_HOST_CMD */
+#define MTX_TO_HOST_CMD 0x0034
+#define MTX_TO_HOST_CMD_ADDR ((hpriv->uccp_mem_addr) + \
+				    MTX_TO_HOST_CMD)
+
+/* Register HOST_TO_MTX_ACK */
+#define HOST_TO_MTX_ACK 0x0038
+#define HOST_TO_MTX_ACK_ADDR ((hpriv->uccp_mem_addr) + \
+				    HOST_TO_MTX_ACK)
+#define MTX_INT_CLR_SHIFT 31
+
+/* Register MTX_TO_HOST_ACK */
+#define MTX_TO_HOST_ACK 0x003C
+#define MTX_TO_HOST_ACK_ADDR ((hpriv->uccp_mem_addr) + \
+				    MTX_TO_HOST_ACK)
+
+/* Register MTX_INT_ENABLE
+ * Enable INT line within META Block
+ */
+#define MTX_INT_ENABLE 0x0044
+#define MTX_INT_ENABLE_ADDR ((hpriv->uccp_mem_addr) + \
+				   MTX_INT_ENABLE)
+#define MTX_INT_EN_SHIFT 31
+
+/* System Level Interrupt Control for each block.
+ * Enable INT line for META block.
+ */
+#define SYS_INT_ENAB 0x0000
+#define SYS_INT_ENAB_ADDR ((hpriv->uccp_mem_addr) + SYS_INT_ENAB)
+#define SYS_INT_MTX_IRQ_ENAB_SHIFT 15
+
+/*********************************************************************
+ */