Clint interrupts virtualization #199
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To verify correctness of interrupt virtualization, we should test some corner cases that are not currently addressed by firmware payloads This tests verify that for virtualized m-mode interrupts from CLINT (timer&software) priority is right (e.g if two interrupts are pending simultaniously, MSI will be delivered before MTI), interrupt will be raised again if not cleared in trap handler, and that MSIs work overall (albeit that should already be covered by zephyr)
Works in CI, doesn't work on the board
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Draft PR: Hopefully partially solves #186 (MEI is yet to implement).