Fix -d instr for Arm32

In 32-bit mode, the PC field is unused and regs[15] is used instead.
CTSRD-CHERI · May 31, 2024 · 6fc0bf7 · 6fc0bf7
1 parent fe6a2d5
commit 6fc0bf7
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Showing 5 changed files with 18 additions and 14 deletions.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
@@ -4661,7 +4661,7 @@ static inline target_ulong cpu_get_recent_pc(CPUArchState *env)
 #ifdef TARGET_CHERI
     return env->pc.cap._cr_cursor;
 #else
-    return env->pc;
+    return is_a64(env) ? env->pc : env->regs[15];
 #endif
 }
 

diff --git a/target/arm/helper-cheri.h b/target/arm/helper-cheri.h
@@ -28,10 +28,6 @@
  * SUCH DAMAGE.
  */
 
-#ifdef CONFIG_TCG_LOG_INSTR
-DEF_HELPER_FLAGS_3(arm_log_instr, TCG_CALL_NO_WG, void, env, tl, i32)
-#endif
-
 DEF_HELPER_5(load_cap_pair_via_cap, void, env, i32, i32, i32, tl)
 DEF_HELPER_5(store_cap_pair_via_cap, void, env, i32, i32, i32, tl)
 

diff --git a/target/arm/helper.c b/target/arm/helper.c
@@ -10410,7 +10410,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     qemu_log_instr_dbg_reg(env, SPSR_NAMES[new_el], old_mode);
 #endif
 
-    qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
+    qemu_log_mask(CPU_LOG_INT, "...with ELR 0x" TARGET_FMT_lx "\n",
                   get_aarch_reg_as_x(&env->elr_el[new_el]));
 
     // NZCV is preserved on exception
@@ -10473,8 +10473,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
 
     qemu_maybe_log_instr_extra(env, "Took exception to EL%d. PSTATE: 0x%x\n",
                                new_el, pstate_read(env));
-    qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
-                  new_el, get_aarch_reg_as_x(&env->pc), pstate_read(env));
+    qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x" TARGET_FMT_lx " PSTATE 0x%x\n",
+                  new_el, cpu_get_recent_pc(env), pstate_read(env));
 
     qemu_log_instr_mode_switch(env, arm_el_to_logging_mode(env, new_el),
                                get_aarch_reg_as_x(&env->pc));
@@ -10495,7 +10495,7 @@ static void handle_semihosting(CPUState *cs)
 
     if (is_a64(env)) {
         qemu_log_mask(CPU_LOG_INT,
-                      "...handling as semihosting call 0x%" PRIx64 "\n",
+                      "...handling as semihosting call 0x" TARGET_FMT_lx "\n",
                       arm_get_xreg(env, 0));
         arm_set_xreg(env, 0, do_common_semihosting(cs));
         increment_aarch_reg(&env->pc, 4);
@@ -14032,17 +14032,12 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
 }
 #endif
 
-#ifdef TARGET_CHERI
-
 #ifdef CONFIG_TCG_LOG_INSTR
-
 void HELPER(arm_log_instr)(CPUARMState *env, target_ulong pc, uint32_t opcode)
 {
     if (qemu_log_instr_enabled(env)) {
         qemu_log_instr_asid(env, cpu_get_asid(env, pc));
         qemu_log_instr(env, pc, (char *)&opcode, sizeof(opcode));
     }
 }
-
-#endif
 #endif
diff --git a/target/arm/helper.h b/target/arm/helper.h
@@ -937,6 +937,10 @@ DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG,
 #include "helper-sve.h"
 #endif
 
+#ifdef CONFIG_TCG_LOG_INSTR
+DEF_HELPER_FLAGS_3(arm_log_instr, TCG_CALL_NO_WG, void, env, tl, i32)
+#endif
+
 #ifdef TARGET_CHERI
 #include "helper-cheri.h"
 #endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
@@ -9107,6 +9107,15 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
     dc->insn = insn;
     dc->base.pc_next += 4;
+
+#if defined(CONFIG_TCG_LOG_INSTR)
+    if (unlikely(dcbase->log_instr_enabled)) {
+        TCGv pc = tcg_const_tl(dcbase->pc_next);
+        gen_helper_arm_log_instr(cpu_env, pc, tcg_constant_i32(insn));
+        tcg_temp_free(pc);
+    }
+#endif
+
     disas_arm_insn(dc, insn);
 
     arm_post_translate_insn(dc);