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Add landing pad unit
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@emanueleparisi
emanueleparisi committed Oct 19, 2024
1 parent b42a348 commit 2a89fdf
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Showing 10 changed files with 334 additions and 26 deletions.
2 changes: 2 additions & 0 deletions Bender.yml
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Expand Up @@ -220,6 +220,8 @@ sources:
# Note: depends on fpnew_pkg, above
- core/fpu_wrap.sv
- core/branch_unit.sv
- core/lpad_port.sv
- core/lpad_unit.sv
- core/compressed_decoder.sv
- core/controller.sv
- core/csr_buffer.sv
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6 changes: 6 additions & 0 deletions core/alu.sv
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Expand Up @@ -360,5 +360,11 @@ module alu
default: ; // default case to suppress unique warning
endcase
end
if (CVA6Cfg.ZiCfiLPEn) begin
unique case (fu_data_i.operation)
ZICFI_LPAD: result_o = fu_data_i.operand_b;
default: ; // default case to suppress unique warning
endcase
end
end
endmodule
88 changes: 87 additions & 1 deletion core/csr_regfile.sv
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Expand Up @@ -181,6 +181,12 @@ module csr_regfile
output riscv::pmpcfg_t [15:0] pmpcfg_o,
// PMP addresses - ACC_DISPATCHER
output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,
// Zicfilp Landing Pad Enable
output logic lpe_o,
// Zicfilp Expected Landing Pad (D)
input elp_t elp_i,
// Zicfilp Expected Landing Pad (Q)
output elp_t elp_o,
// TO_BE_COMPLETED - PERF_COUNTERS
output logic [31:0] mcountinhibit_o
);
Expand Down Expand Up @@ -280,6 +286,8 @@ module csr_regfile
logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q;
logic [3:0] index;

elp_t elp_d, elp_q;

localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
| (riscv::XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
| (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
Expand Down Expand Up @@ -944,6 +952,7 @@ module csr_regfile
menvcfg_d = menvcfg_q;
henvcfg_d = henvcfg_q;
senvcfg_d = senvcfg_q;
mseccfg_d = mseccfg_q;
dcache_d = dcache_q;
icache_d = icache_q;
acc_cons_d = acc_cons_q;
Expand Down Expand Up @@ -2129,6 +2138,69 @@ module csr_regfile
// actually return from debug mode
debug_mode_d = 1'b0;
end

// ----------------
// Landing Pad
// ----------------
if (CVA6Cfg.ZiCfiLPEn) begin
// Enable landing pad.
// TODO(emanueleparisi) Do not consider H-mode for now.
if (CVA6Cfg.RVS) begin
unique case (priv_lvl_q)
riscv::PRIV_LVL_M: lpe_o = mseccfg_q.mlpe;
riscv::PRIV_LVL_S: lpe_o = menvcfg_q.lpe;
riscv::PRIV_LVL_U: lpe_o = senvcfg_q.lpe;
default: lpe_o = 'b0;
endcase
end else begin
unique case (priv_lvl_q)
riscv::PRIV_LVL_M: lpe_o = mseccfg_q.mlpe;
riscv::PRIV_LVL_U: lpe_o = menvcfg_q.lpe;
default: lpe_o = 'b0;
endcase
end

// Assign ELP flag.
// TODO(emanueleparisi) Do not consider H-mode for now.
elp_d = elp_i;
if (ex_i.valid) begin
elp_d = NO_LPAD_EXPECTED;
end
if (mret) begin
elp_d = elp_t'(mstatus_q.mpelp);
end
if (CVA6Cfg.RVS && sret) begin
elp_d = elp_t'(mstatus_d.spelp);
end

// Assign xPELP flags.
// TODO(emanueleparisi) Do not consider H-mode for now.
//mstatus_d.mpelp = elp_t'(mstatus_q.mpelp);
//mstatus_d.spelp = elp_t'(mstatus_q.spelp);
if (ex_i.valid) begin
if (priv_lvl_d == riscv::PRIV_LVL_M) begin
mstatus_d.mpelp = elp_i;
end else if (CVA6Cfg.RVS && priv_lvl_d == riscv::PRIV_LVL_S) begin
mstatus_d.spelp = elp_i;
end
end
if (mret) begin
if (priv_lvl_d == riscv::PRIV_LVL_M) begin
mstatus_d.mpelp = NO_LPAD_EXPECTED;
end else if (CVA6Cfg.RVS && priv_lvl_d == riscv::PRIV_LVL_S) begin
mstatus_d.spelp = NO_LPAD_EXPECTED;
end
end
if (CVA6Cfg.RVS && sret) begin
if (priv_lvl_d == riscv::PRIV_LVL_S) begin
mstatus_d.spelp = NO_LPAD_EXPECTED;
end
end
end else begin
lpe_o = 'b0;
elp_d = NO_LPAD_EXPECTED;
end

end

// ---------------------------
Expand Down Expand Up @@ -2383,6 +2455,9 @@ module csr_regfile
end
default: ;
endcase

// Zicfilp
elp_o = elp_q;
end

// in debug mode we execute with privilege level M
Expand Down Expand Up @@ -2476,6 +2551,7 @@ module csr_regfile
menvcfg_q <= 'b0;
henvcfg_q <= 'b0;
senvcfg_q <= 'b0;
mseccfg_q <= 'b0;
dcache_q <= {{riscv::XLEN - 1{1'b0}}, 1'b1};
icache_q <= {{riscv::XLEN - 1{1'b0}}, 1'b1};
mcountinhibit_q <= '0;
Expand Down Expand Up @@ -2534,6 +2610,11 @@ module csr_regfile
pmpaddr_q[i] <= '0;
end
end

// Zicfilp
if (CVA6Cfg.ZiCfiLPEn) begin
elp_q <= NO_LPAD_EXPECTED;
end
end else begin
priv_lvl_q <= priv_lvl_d;
// floating-point registers
Expand Down Expand Up @@ -2562,7 +2643,8 @@ module csr_regfile
if (CVA6Cfg.TvalEn) mtval_q <= mtval_d;
menvcfg_q <= menvcfg_d;
henvcfg_q <= henvcfg_d;
senvcfg_q <= senvcfg_d;
senvcfg_q <= senvcfg_d;
mseccfg_q <= mseccfg_d;
dcache_q <= dcache_d;
icache_q <= icache_d;
mcountinhibit_q <= mcountinhibit_d;
Expand Down Expand Up @@ -2630,6 +2712,10 @@ module csr_regfile
pmpaddr_q[i] <= '0;
end
end
// Zicfilp
if (CVA6Cfg.ZiCfiLPEn) begin
elp_q <= elp_d;
end
end
end

Expand Down
78 changes: 57 additions & 21 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -201,7 +201,7 @@ module cva6
CVA6Cfg.XFVec,
CVA6Cfg.CvxifEn,
CVA6Cfg.ZiCondExtEn,
//CVA6Cfg.ZiCfiLPEn,
CVA6Cfg.ZiCfiLPEn,
CVA6Cfg.RVSCLIC,
// Extended
bit'(RVF),
Expand Down Expand Up @@ -376,6 +376,15 @@ module cva6
logic amo_valid_commit;
// ACCEL Commit
logic acc_valid_acc_ex;
// --------------
// ID <-> LP
// --------------
scoreboard_entry_t [CVA6ExtendCfg.NrCommitPorts-1:0] commit_instr_id_lp;
// --------------
// LP <-> COMMIT
// --------------
scoreboard_entry_t [CVA6ExtendCfg.NrCommitPorts-1:0] commit_instr_lp_commit;

// --------------
// ID <-> COMMIT
// --------------
Expand Down Expand Up @@ -444,6 +453,9 @@ module cva6
riscv::pmpcfg_t [15:0] pmpcfg;
logic [15:0][riscv::PLEN-3:0] pmpaddr;
logic [31:0] mcountinhibit_csr_perf;
logic lpe_csr_lp;
elp_t elp_csr_lp;
elp_t elp_lp_csr;
// ----------------------------
// Performance Counters <-> *
// ----------------------------
Expand Down Expand Up @@ -735,7 +747,7 @@ module cva6
.wdata_i (wdata_commit_id),
.we_gpr_i (we_gpr_commit_id),
.we_fpr_i (we_fpr_commit_id),
.commit_instr_o (commit_instr_id_commit),
.commit_instr_o (commit_instr_id_lp),
.commit_ack_i (commit_ack),
// Performance Counters
.stall_issue_o (stall_issue),
Expand Down Expand Up @@ -869,6 +881,27 @@ module cva6
.rvfi_mem_paddr_o (rvfi_mem_paddr)
);


// ------------
// Landing Pad
// ------------

if (CVA6Cfg.ZiCfiLPEn) begin : gen_landingpad_ports
lpad_unit #(
.CVA6Cfg(CVA6ExtendCfg)
) lpad_unit_i (
.clk_i ( clk_i ),
.rst_ni ( rst_uarch_n ),
.lpe_i ( lpe_csr_lp ),
.elp_i ( elp_csr_lp ),
.commit_instr_i ( commit_instr_id_lp ),
.elp_o ( elp_lp_csr ),
.commit_instr_o ( commit_instr_lp_commit )
);
end else begin
assign commit_instr_lp_commit = commit_instr_id_lp;
end

// ---------
// Commit
// ---------
Expand All @@ -887,7 +920,7 @@ module cva6
.exception_o (ex_commit),
.dirty_fp_state_o (dirty_fp_state),
.single_step_i (single_step_csr_commit),
.commit_instr_i (commit_instr_id_commit),
.commit_instr_i (commit_instr_lp_commit),
.commit_ack_o (commit_ack),
.no_st_pending_i (no_st_pending_commit),
.waddr_o (waddr_commit_id),
Expand Down Expand Up @@ -927,7 +960,7 @@ module cva6
) csr_regfile_i (
.flush_o (flush_csr_ctrl),
.halt_csr_o (halt_csr_ctrl),
.commit_instr_i (commit_instr_id_commit),
.commit_instr_i (commit_instr_lp_commit),
.commit_ack_i (commit_ack),
.boot_addr_i (boot_addr_i[riscv::VLEN-1:0]),
.hart_id_i (hart_id_i[riscv::XLEN-1:0]),
Expand Down Expand Up @@ -998,6 +1031,9 @@ module cva6
.perf_we_o (we_csr_perf),
.pmpcfg_o (pmpcfg),
.pmpaddr_o (pmpaddr),
.lpe_o (lpe_csr_lp),
.elp_i (elp_lp_csr),
.elp_o (elp_csr_lp),
.mcountinhibit_o (mcountinhibit_csr_perf),
.debug_req_i,
.ipi_i,
Expand All @@ -1021,7 +1057,7 @@ module cva6
.we_i (we_csr_perf),
.data_i (data_csr_perf),
.data_o (data_perf_csr),
.commit_instr_i(commit_instr_id_commit),
.commit_instr_i(commit_instr_lp_commit),
.commit_ack_i (commit_ack),

.l1_icache_miss_i (icache_miss_cache_perf),
Expand Down Expand Up @@ -1324,7 +1360,7 @@ module cva6
.issue_instr_hs_i (issue_instr_hs_id_acc),
.issue_stall_o (stall_acc_id),
.fu_data_i (fu_data_id_ex),
.commit_instr_i (commit_instr_id_commit),
.commit_instr_i (commit_instr_lp_commit),
.commit_st_barrier_i (fence_i_commit_controller | fence_commit_controller),
.acc_trans_id_o (acc_trans_id_ex_id),
.acc_result_o (acc_result_ex_id),
Expand Down Expand Up @@ -1438,8 +1474,8 @@ module cva6
.full_o (),
.empty_o (pc_empty[i]),
.usage_o (),
.data_i (commit_instr_id_commit[i].pc),
.push_i (commit_ack[i] & ~commit_instr_id_commit[i].ex.valid),
.data_i (commit_instr_lp_commit[i].pc),
.push_i (commit_ack[i] & ~commit_instr_lp_commit[i].ex.valid),
.data_o (pc_data[i]),
.pop_i (pc_pop[i])
);
Expand Down Expand Up @@ -1483,7 +1519,7 @@ module cva6
assign tracer_if.we_gpr = we_gpr_commit_id;
assign tracer_if.we_fpr = we_fpr_commit_id;
// commit
assign tracer_if.commit_instr = commit_instr_id_commit;
assign tracer_if.commit_instr = commit_instr_lp_commit;
assign tracer_if.commit_ack = commit_ack;
// branch predict
assign tracer_if.resolve_branch = resolved_branch;
Expand Down Expand Up @@ -1533,22 +1569,22 @@ module cva6
endcase
end
for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin
if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode,
commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]);
end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin
if (commit_instr_id_commit[i].ex.cause == 2) begin
if (commit_ack[i] && !commit_instr_lp_commit[i].ex.valid) begin
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_lp_commit[i].pc, mode,
commit_instr_lp_commit[i].ex.tval[31:0], commit_instr_lp_commit[i].ex.tval[31:0]);
end else if (commit_ack[i] && commit_instr_lp_commit[i].ex.valid) begin
if (commit_instr_lp_commit[i].ex.cause == 2) begin
$fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n",
commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc);
commit_instr_lp_commit[i].ex.tval[31:0], commit_instr_lp_commit[i].pc);
end else begin
if (CVA6Cfg.DebugEn && debug_mode) begin
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc,
mode, commit_instr_id_commit[i].ex.tval[31:0],
commit_instr_id_commit[i].ex.tval[31:0]);
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_lp_commit[i].pc,
mode, commit_instr_lp_commit[i].ex.tval[31:0],
commit_instr_lp_commit[i].ex.tval[31:0]);
end else begin
$fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n",
commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].ex.tval[31:0],
commit_instr_id_commit[i].pc);
commit_instr_lp_commit[i].ex.cause, commit_instr_lp_commit[i].ex.tval[31:0],
commit_instr_lp_commit[i].pc);
end
end
end
Expand Down Expand Up @@ -1587,7 +1623,7 @@ module cva6
.rs1_forwarding_i(rs1_forwarding_id_ex),
.rs2_forwarding_i(rs2_forwarding_id_ex),

.commit_instr_i(commit_instr_id_commit),
.commit_instr_i(commit_instr_lp_commit),
.ex_commit_i (ex_commit),
.priv_lvl_i (priv_lvl),

Expand Down
1 change: 1 addition & 0 deletions core/decoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1368,6 +1368,7 @@ module decoder
imm_select = UIMM;
instruction_o.use_pc = 1'b1;
instruction_o.rd[4:0] = instr.utype.rd;
if (CVA6Cfg.ZiCfiLPEn && instr.utype.rd == 'b0) instruction_o.op = ZICFI_LPAD;
end

riscv::OpcodeLui: begin
Expand Down
19 changes: 18 additions & 1 deletion core/include/ariane_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -598,7 +598,9 @@ package ariane_pkg;
ACCEL_OP_STORE,
// Zicond instruction
CZERO_EQZ,
CZERO_NEZ
CZERO_NEZ,
// Zicfi instruction
ZICFI_LPAD
} fu_op;

typedef struct packed {
Expand Down Expand Up @@ -750,6 +752,21 @@ package ariane_pkg;
logic vfp; // is this a vector floating-point instruction?
} scoreboard_entry_t;

// ---------------
// Landing Pad Unit
// ---------------

typedef enum logic {
NO_LPAD_EXPECTED = 1'b0,
LPAD_EXPECTED = 1'b1
} elp_t;

localparam LPAD_LABEL_BITS = 20;
typedef logic [LPAD_LABEL_BITS-1:0] lpl_t;

localparam logic [riscv::XLEN-1:0] LPAD_EXCEPTION_CAUSE = 18;
localparam logic [riscv::XLEN-1:0] LPAD_EXCEPTION_TVAL = 2;

// ---------------
// MMU instanciation
// ---------------
Expand Down
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