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Update version and docs for 5.0.0 (#508)
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# 5.x series change log | ||
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This page summarizes the major functional and performance changes in each | ||
release of the 5.x series. | ||
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All performance data on this page is measured on an Intel Core i5-9600K | ||
clocked at 4.2 GHz, running `astcenc` using AVX2 and 6 threads. | ||
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<!-- ---------------------------------------------------------------------- --> | ||
## 5.0.0 | ||
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**Status:** November 2024 | ||
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The 5.0.0 release is the first stable release in the 5.x series. The main new | ||
feature is support for the Arm Scalable Vector Extensions (SVE) SIMD instruction | ||
set. | ||
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* **General:** | ||
* **Bug fix:** Fixed incorrect return type in "None" vector library | ||
reference implementation. | ||
* **Bug fix:** Fixed sincos table index under/overflow. | ||
* **Feature:** Changed `ASTCENC_ISA_NATIVE` builds to use `-march=native` and | ||
`-mcpu=native`. | ||
* **Feature:** Added backend for Arm SVE fixed-width 256-bit builds. These | ||
can only run on hardware implementing 256-bit SVE. | ||
* **Feature:** Added backend for Arm SVE 128-bit builds. These are portable | ||
builds and can run on hardware implementing any SVE vector length, but the | ||
explicit SVE use is augmented NEON and will only use the bottom 128-bits of | ||
each SVE vector. | ||
* **Feature:** Optimized NEON mask `any()` and `all()` functions. | ||
* **Feature:** Migrated build and test to GitHub Actions pipelines. | ||
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_Copyright © 2022-2024, Arm Limited and contributors. All rights reserved._ |
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