diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.board b/boards/xtensa/xiao_esp32s3/Kconfig.board new file mode 100644 index 00000000000000..aa4b08ecf0f06f --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/Kconfig.board @@ -0,0 +1,8 @@ +# XIAO ESP32S3 board configuration + +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32S3 + bool "XIAO ESP32S3 Board" + depends on SOC_ESP32S3 diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.defconfig b/boards/xtensa/xiao_esp32s3/Kconfig.defconfig new file mode 100644 index 00000000000000..4a1b168cf54a0c --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "xiao_esp32s3" + depends on BOARD_XIAO_ESP32S3 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_SIZE + default 98304 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.sysbuild b/boards/xtensa/xiao_esp32s3/Kconfig.sysbuild new file mode 100644 index 00000000000000..3a2d17ac5cfd06 --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/xtensa/xiao_esp32s3/board.cmake b/boards/xtensa/xiao_esp32s3/board.cmake new file mode 100644 index 00000000000000..2f04d1fe8861ea --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg b/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg new file mode 100644 index 00000000000000..ede72715582987 Binary files /dev/null and b/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg differ diff --git a/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg b/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg new file mode 100644 index 00000000000000..41d9bf4bbb80d5 Binary files /dev/null and b/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg differ diff --git a/boards/xtensa/xiao_esp32s3/doc/index.rst b/boards/xtensa/xiao_esp32s3/doc/index.rst new file mode 100644 index 00000000000000..1f12763646b0a1 --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/doc/index.rst @@ -0,0 +1,239 @@ +.. _xiao_esp32s3: + +XIAO ESP32S3 +############ + +Overview +******** + +Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the +Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. + +For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. + +.. figure:: img/xiao_esp32s3.jpg + :align: center + :alt: XIAO ESP32S3 + + XIAO ESP32S3 + +Hardware +******** + +This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an U.FL external antenna connector. It is based on a standard XIAO 14 pin +pinout. + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +Supported Features +================== + +Current Zephyr's XIAO ESP32S3 board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ + +Connections and IOs +=================== + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32s3_pinout.jpg + :align: center + :alt: XIAO ESP32S3 Pinout + + XIAO ESP32S3 Pinout + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the EPS32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: xiao_esp32s3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3 + :goals: build + +The usual ``flash`` target will work with the ``xiao_esp32s3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3 + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32s3 + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3 + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3 + :goals: debug +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ diff --git a/boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi b/boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi new file mode 100644 index 00000000000000..2251ed92015a41 --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + xiao_d: connector { + compatible = "seeed,xiao-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 1 0>, /* D0 */ + <1 0 &gpio0 2 0>, /* D1 */ + <2 0 &gpio0 3 0>, /* D2 */ + <3 0 &gpio0 4 0>, /* D3 */ + <4 0 &gpio0 5 0>, /* D4 */ + <5 0 &gpio0 6 0>, /* D5 */ + <6 0 &gpio0 43 0>, /* D6 */ + <7 0 &gpio0 44 0>, /* D7 */ + <8 0 &gpio0 7 0>, /* D8 */ + <9 0 &gpio0 8 0>, /* D9 */ + <10 0 &gpio0 9 0>; /* D10 */ + }; +}; + +xiao_spi: &spi2 {}; +xiao_i2c: &i2c0 {}; +xiao_serial: &uart0 {}; diff --git a/boards/xtensa/xiao_esp32s3/support/openocd.cfg b/boards/xtensa/xiao_esp32s3/support/openocd.cfg new file mode 100644 index 00000000000000..2f740b4a36ab1f --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi b/boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi new file mode 100644 index 00000000000000..3f9343d846ef82 --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright 2022 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts new file mode 100644 index 00000000000000..667cabab6ed9de --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_esp32s3-pinctrl.dtsi" +#include "seeed_xiao_connector.dtsi" + +/ { + model = "Seeed XIAO ESP32S3"; + compatible = "seeed,xiao-esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + led0 = &led0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "BUILTIN LED"; + }; + }; + +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml new file mode 100644 index 00000000000000..129b25ed8ded21 --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml @@ -0,0 +1,20 @@ +identifier: xiao_esp32s3 +name: XIAO ESP32S3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig b/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig new file mode 100644 index 00000000000000..df75dd7d28367b --- /dev/null +++ b/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XTENSA_RESET_VECTOR=n +CONFIG_BOARD_XIAO_ESP32S3=y +CONFIG_SOC_ESP32S3=y +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XTENSA_USE_CORE_CRT1=n +CONFIG_GPIO=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_CLOCK_CONTROL=y diff --git a/samples/basic/blinky_pwm/boards/xiao_esp32s3.overlay b/samples/basic/blinky_pwm/boards/xiao_esp32s3.overlay new file mode 100644 index 00000000000000..045056613e0804 --- /dev/null +++ b/samples/basic/blinky_pwm/boards/xiao_esp32s3.overlay @@ -0,0 +1,44 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + */ + +#include +#include + +/ { + aliases { + pwm-0 = &ledc0; + pwm-led0 = &pwm_led_blue; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led_blue: pwm_led_gpio0_21 { + label = "PWM LED0"; + pwms = <&ledc0 0 1000 PWM_POLARITY_NORMAL>; + }; + }; +}; + +&pinctrl { + ledc0_default: ledc0_default { + group1 { + pinmux = ; + output-enable; + }; + }; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; +}; diff --git a/samples/net/wifi/boards/xiao_esp32s3.conf b/samples/net/wifi/boards/xiao_esp32s3.conf new file mode 100644 index 00000000000000..a72fdf39efa245 --- /dev/null +++ b/samples/net/wifi/boards/xiao_esp32s3.conf @@ -0,0 +1,11 @@ +CONFIG_WIFI=y + +CONFIG_NETWORKING=y +CONFIG_NET_L2_ETHERNET=y + +CONFIG_NET_IPV6=n +CONFIG_NET_IPV4=y +CONFIG_NET_DHCPV4=y +CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y + +CONFIG_NET_LOG=y diff --git a/samples/net/wifi/boards/xiao_esp32s3.overlay b/samples/net/wifi/boards/xiao_esp32s3.overlay new file mode 100644 index 00000000000000..4d69fe29493052 --- /dev/null +++ b/samples/net/wifi/boards/xiao_esp32s3.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&wifi { + status = "okay"; +};