diff --git a/boards/nxp/frdm_mcxa156/CMakeLists.txt b/boards/nxp/frdm_mcxa156/CMakeLists.txt new file mode 100644 index 000000000000000..df4c3939ca79370 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/frdm_mcxa156/Kconfig b/boards/nxp/frdm_mcxa156/Kconfig new file mode 100644 index 000000000000000..23271bc179f9711 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/Kconfig @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 1 + help + Board initialization priority. diff --git a/boards/nxp/frdm_mcxa156/Kconfig.frdm_mcxa156 b/boards/nxp/frdm_mcxa156/Kconfig.frdm_mcxa156 new file mode 100644 index 000000000000000..7c90d7cb0d872e0 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/Kconfig.frdm_mcxa156 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA156 + select SOC_MCXA156 if BOARD_FRDM_MCXA156 + select SOC_PART_NUMBER_MCXA156VLL diff --git a/boards/nxp/frdm_mcxa156/board.c b/boards/nxp/frdm_mcxa156/board.c new file mode 100644 index 000000000000000..98801c47a1a2378 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/board.c @@ -0,0 +1,125 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include + +/* Core clock frequency: 150MHz */ +#define CLOCK_INIT_CORE_CLOCK 960000000U +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +static int frdm_mcxa156_init(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = + (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = + (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(porta), okay) + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(portb), okay) + RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(portc), okay) + RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(portd), okay) + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(porte), okay) + RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay) + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) + RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) + RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) + RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay) + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART0); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + + return 0; +} + +SYS_INIT(frdm_mcxa156_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/nxp/frdm_mcxa156/board.cmake b/boards/nxp/frdm_mcxa156/board.cmake new file mode 100644 index 000000000000000..a9b42d72ac334b4 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXA156") +board_runner_args(linkserver "--device=MCXA156:FRDM-MCXA156") +board_runner_args(pyocd "--target=mcxA156") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/frdm_mcxa156/board.yml b/boards/nxp/frdm_mcxa156/board.yml new file mode 100644 index 000000000000000..fd3cb5a5c6d9413 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_mcxa156 + vendor: nxp + socs: + - name: mcxa156 diff --git a/boards/nxp/frdm_mcxa156/doc/frdm_mcxa156.webp b/boards/nxp/frdm_mcxa156/doc/frdm_mcxa156.webp new file mode 100644 index 000000000000000..4261ce082ed6220 Binary files /dev/null and b/boards/nxp/frdm_mcxa156/doc/frdm_mcxa156.webp differ diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst new file mode 100644 index 000000000000000..96255473c2f1b50 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/doc/index.rst @@ -0,0 +1,204 @@ +.. _frdm_mcxa156: + +NXP FRDM-MCXA156 +################ + +Overview +******** + +FRDM-MCXA156 are compact and scalable development boards for rapid prototyping of +MCX A15X MCUs. They offer industry standard headers for easy access to the +MCUs I/Os, integrated open-standard serial interfaces, external flash memory and +an on-board MCU-Link debugger. MCX N Series are high-performance, low-power +microcontrollers with intelligent peripherals and accelerators providing multi-tasking +capabilities and performance efficiency. + +.. image:: frdm_mcxa156.webp + :align: center + :alt: FRDM-MCXA156 + +Hardware +******** + +- MCX-A156 Arm Cortex-M33 microcontroller running at 96 MHz +- 1MB dual-bank on chip Flash +- 128 KB RAM +- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors +- 2x FlexCAN with FD, 2x I3Cs, 2x SAI +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS + +For more information about the MCX-A156 SoC and FRDM-MCXA156 board, see: + +- `MCX-A156 SoC Website`_ +- `MCX-A156 Datasheet`_ +- `MCX-A156 Reference Manual`_ +- `FRDM-MCXA156 Website`_ +- `FRDM-MCXA156 User Guide`_ +- `FRDM-MCXA156 Board User Manual`_ +- `FRDM-MCXA156 Schematics`_ + +Supported Features +================== + +The FRDM-MCXA156 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ + +Targets available +================== + +The default configuration file +:zephyr_file:`boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MCX-A156 SoC has 5 gpio controllers and has pinmux registers which +can be used to configure the functionality of a pin. + ++------------+-----------------+----------------------------+ +| Name | Function | Usage | ++============+=================+============================+ +| PIO0_2 | UART | UART RX | ++------------+-----------------+----------------------------+ +| PIO0_3 | UART | UART TX | ++------------+-----------------+----------------------------+ + +System Clock +============ + +The MCX-A156 SoC is configured to use FRO running at 96MHz as a source for +the system clock. + +Serial Port +=========== + +The FRDM-MCXA156 SoC has 5 LPUART interfaces for serial communication. +LPUART 0 is configured as UART for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``DFU mode`` to program the firmware, +short jumper JP5. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``DFU mode`` +by shortening the jumper JP5. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J24) of the board. Additionally, the jumper JP7 must +be shortened. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J21, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa156 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa156/mcxa156 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa156/mcxa156 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa156/mcxa156 + +.. _MCX-A156 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X + +.. _MCX-A156 Datasheet: + https://www.nxp.com/docs/en/data-sheet/MCXAP100M96FS6.pdf + +.. _MCX-A156 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MCXAP100M96FS6RM + +.. _FRDM-MCXA156 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA156 + +.. _FRDM-MCXA156 User Guide: + https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa156:GS-FRDM-MCXA156 + +.. _FRDM-MCXA156 Board User Manual: + https://www.nxp.com/docs/en/user-manual/UM12121.pdf + +.. _FRDM-MCXA156 Schematics: + https://www.nxp.com/webapp/Download?colCode=SPF-90841 diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi new file mode 100644 index 000000000000000..a4e241c1bfea84f --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + pinmux_lpuart0: pinmux_lpuart0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts new file mode 100644 index 000000000000000..73c872a0337abf9 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts @@ -0,0 +1,90 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxa156-pinctrl.dtsi" +#include + +/ { + model = "NXP FRDM_MCXA156 board"; + compatible = "nxp,mcxa156", "nxp,mcx"; + + aliases{ + led0 = &red_led; + led1 = &green_led; + led2 = &red_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + green_led: led_1 { + gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + blue_led: led_2 { + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_2 { + label = "User SW2"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_3: button_3 { + label = "User SW3"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml new file mode 100644 index 000000000000000..c7809e4548b10c8 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxa156 +name: NXP FRDM MCXA156 +type: mcu +arch: arm +ram: 128 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: nxp diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig new file mode 100644 index 000000000000000..3fc86cf38dc7ad7 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig @@ -0,0 +1,12 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y