From bd3bc4b704bde393e5a4f915337e1f487f240cc1 Mon Sep 17 00:00:00 2001 From: Marcio Ribeiro Date: Wed, 7 Feb 2024 17:45:25 -0300 Subject: [PATCH] driver: i2s: esp32s3/esp32c3 i2s support added for esp32s3 and esp32c3 Signed-off-by: Marcio Ribeiro --- .../esp32c3_devkitm-pinctrl.dtsi | 14 + .../esp32c3_devkitm/esp32c3_devkitm.dts | 6 + .../esp32c3_devkitm/esp32c3_devkitm.yaml | 1 + .../esp32s3_devkitc-pinctrl.dtsi | 32 + .../esp32s3_devkitc_procpu.dts | 12 + .../esp32s3_devkitc_procpu.yaml | 1 + .../esp32s3_devkitm-pinctrl.dtsi | 32 + .../esp32s3_devkitm_procpu.dts | 12 + .../esp32s3_devkitm_procpu.yaml | 1 + drivers/i2s/CMakeLists.txt | 1 + drivers/i2s/Kconfig.esp32 | 28 + drivers/i2s/i2s_esp32.c | 942 ++++++++ drivers/i2s/i2s_esp32.h | 67 + dts/bindings/i2s/espressif,esp32-i2s.yaml | 18 + .../espressif/esp32c3/esp32c3_common.dtsi | 11 + .../espressif/esp32s3/esp32s3_common.dtsi | 22 + .../dt-bindings/pinctrl/esp32c3-pinctrl.h | 469 ++++ .../dt-bindings/pinctrl/esp32s3-pinctrl.h | 1904 +++++++++++++++++ west.yml | 2 +- 19 files changed, 3574 insertions(+), 1 deletion(-) create mode 100644 drivers/i2s/Kconfig.esp32 create mode 100644 drivers/i2s/i2s_esp32.c create mode 100644 drivers/i2s/i2s_esp32.h create mode 100644 dts/bindings/i2s/espressif,esp32-i2s.yaml diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi index 29969c8da3773e5..6012ffcd970902f 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi @@ -43,6 +43,20 @@ }; }; + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + twai_default: twai_default { group1 { pinmux = , diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index ae11ed41aa2e258..da65b614c08f77b 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -58,6 +58,12 @@ pinctrl-names = "default"; }; +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &trng0 { status = "okay"; }; diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml index a2c88796ca38ca8..49ba690a56348d4 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml @@ -8,6 +8,7 @@ supported: - adc - gpio - i2c + - i2s - watchdog - uart - dma diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi index 5f3fbe8b23949ac..2967cce447d433c 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi @@ -40,6 +40,38 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + spim2_default: spim2_default { group1 { pinmux = , diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts index afff520f7ba14c1..39afa2acb6c4ea2 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts @@ -86,6 +86,18 @@ pinctrl-names = "default"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &spi2 { #address-cells = <1>; #size-cells = <0>; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml index c4f589175769631..2a5e48d464f5c1c 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml @@ -8,6 +8,7 @@ supported: - gpio - uart - i2c + - i2s - spi - can - counter diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi index 34fa6e920c6613d..aa048eb4b7ff90c 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi @@ -40,6 +40,38 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + spim2_default: spim2_default { group1 { pinmux = , diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts index 95390a0324bf0a9..81ef3754186609e 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts @@ -82,6 +82,18 @@ pinctrl-names = "default"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &spi2 { #address-cells = <1>; #size-cells = <0>; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml index f9e577353a95d8a..84bc4206e3552aa 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml @@ -8,6 +8,7 @@ supported: - gpio - uart - i2c + - i2s - spi - can - counter diff --git a/drivers/i2s/CMakeLists.txt b/drivers/i2s/CMakeLists.txt index c6f6d17f4f9381a..90b8d737a11ee13 100644 --- a/drivers/i2s/CMakeLists.txt +++ b/drivers/i2s/CMakeLists.txt @@ -12,3 +12,4 @@ zephyr_library_sources_ifdef(CONFIG_I2S_LITEX i2s_litex.c) zephyr_library_sources_ifdef(CONFIG_I2S_MCUX_FLEXCOMM i2s_mcux_flexcomm.c) zephyr_library_sources_ifdef(CONFIG_I2S_NRFX i2s_nrfx.c) zephyr_library_sources_ifdef(CONFIG_I2S_MCUX_SAI i2s_mcux_sai.c) +zephyr_library_sources_ifdef(CONFIG_I2S_ESP32 i2s_esp32.c) diff --git a/drivers/i2s/Kconfig.esp32 b/drivers/i2s/Kconfig.esp32 new file mode 100644 index 000000000000000..4ba3d67a23d1344 --- /dev/null +++ b/drivers/i2s/Kconfig.esp32 @@ -0,0 +1,28 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: Apache-2.0 + +config I2S_ESP32 + bool "ESP32 I2S driver" + default y + depends on DT_HAS_ESPRESSIF_ESP32_I2S_ENABLED + depends on DT_HAS_ESPRESSIF_ESP32_GDMA_ENABLED + select GPIO_ESP32 + help + Enables the ESP32 I2S driver (GDMA SoCs only) + +if I2S_ESP32 + +config I2S_ESP32_RX_BLOCK_COUNT + int "ESP32 I2S RX block count" + default 5 + help + Max number of elements waiting to be read from the I2S RX channel + +config I2S_ESP32_TX_BLOCK_COUNT + int "ESP32 I2S TX block count" + default 5 + help + Max number of elements waiting to be transmitted by the I2S TX channel + +endif diff --git a/drivers/i2s/i2s_esp32.c b/drivers/i2s/i2s_esp32.c new file mode 100644 index 000000000000000..fda28e3163d727f --- /dev/null +++ b/drivers/i2s/i2s_esp32.c @@ -0,0 +1,942 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT espressif_esp32_i2s + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "i2s_esp32.h" + +LOG_MODULE_REGISTER(i2s_esp32, CONFIG_I2S_LOG_LEVEL); + +#if !SOC_GDMA_SUPPORTED +#error "Only SoCs with GDMA peripheral are supported!" +#endif + +#define IS2_ESP32_CLK_SRC I2S_CLK_SRC_DEFAULT + +#define I2S_ESP32_MODULO_INC(val, max) { val = (++val < max) ? val : 0; } + +uint32_t i2s_esp32_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz) +{ + uint32_t clk_freq = 0; + + esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq); + return clk_freq; +} + +static esp_err_t i2s_esp32_calculate_clock(const struct i2s_config *i2s_cfg, + i2s_hal_clock_info_t *i2s_hal_clock_info) +{ + if (i2s_cfg == NULL) { + LOG_ERR("Input i2s_cfg is NULL"); + return ESP_ERR_INVALID_ARG; + } + + if (i2s_hal_clock_info == NULL) { + LOG_ERR("Input hal_clock_info is NULL"); + return ESP_ERR_INVALID_ARG; + } + + /* For words greater than 16-bit the channel length is considered 32-bit */ + const uint8_t channel_length = i2s_cfg->word_size > 16U ? 32U : 16U; + + uint16_t mclk_multiple = 256; + + if (i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE || + i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) { + i2s_hal_clock_info->bclk_div = 8; + i2s_hal_clock_info->bclk = i2s_cfg->frame_clk_freq * i2s_cfg->channels + * channel_length; + i2s_hal_clock_info->mclk = i2s_cfg->frame_clk_freq + * i2s_hal_clock_info->bclk_div; + } else { + i2s_hal_clock_info->bclk = i2s_cfg->frame_clk_freq * i2s_cfg->channels + * channel_length; + i2s_hal_clock_info->mclk = i2s_cfg->frame_clk_freq * mclk_multiple; + i2s_hal_clock_info->bclk_div = i2s_hal_clock_info->mclk + / i2s_hal_clock_info->bclk; + } + + i2s_hal_clock_info->sclk = + i2s_esp32_get_source_clk_freq(IS2_ESP32_CLK_SRC, i2s_hal_clock_info->mclk); + + i2s_hal_clock_info->mclk_div = i2s_hal_clock_info->sclk / + i2s_hal_clock_info->mclk; + if (i2s_hal_clock_info->mclk_div == 0) { + LOG_ERR("Sample rate is too large for the current clock source"); + return ESP_ERR_INVALID_ARG; + } + + return ESP_OK; +} + +static int i2s_esp32_queue_get(struct ring_buffer *rb, void **mem_block, size_t *size) +{ + unsigned int key = irq_lock(); + + if (rb->count == 0) { + irq_unlock(key); + return -ENOMEM; + } + rb->count--; + + *mem_block = rb->array[rb->tail].buffer; + *size = rb->array[rb->tail].size; + I2S_ESP32_MODULO_INC(rb->tail, rb->len); + + irq_unlock(key); + + return 0; +} + +static int i2s_esp32_queue_put(struct ring_buffer *rb, void *mem_block, size_t size) +{ + unsigned int key = irq_lock(); + + if (rb->count == rb->len) { + irq_unlock(key); + return -ENOMEM; + } + rb->count++; + + rb->array[rb->head].buffer = mem_block; + rb->array[rb->head].size = size; + I2S_ESP32_MODULO_INC(rb->head, rb->len); + + irq_unlock(key); + + return 0; +} + +static void i2s_esp32_rx_queue_drop(struct i2s_esp32_stream *stream) +{ + size_t size; + void *mem_block; + + while (i2s_esp32_queue_get(&stream->queue, &mem_block, &size) == 0) { + k_mem_slab_free(stream->i2s_cfg.mem_slab, mem_block); + } + + k_sem_reset(&stream->queue.sem); +} + +static void i2s_esp32_tx_queue_drop(struct i2s_esp32_stream *stream) +{ + size_t size; + void *mem_block; + unsigned int n = 0U; + + while (i2s_esp32_queue_get(&stream->queue, &mem_block, &size) == 0) { + k_mem_slab_free(stream->i2s_cfg.mem_slab, mem_block); + n++; + } + + for (; n > 0; n--) { + k_sem_give(&stream->queue.sem); + } +} + +static void i2s_esp32_rx_callback(const struct device *dma_dev, void *arg, uint32_t channel, + int status); +static void i2s_esp32_tx_callback(const struct device *dma_dev, void *arg, uint32_t channel, + int status); + +static int i2s_esp32_restart_dma(const struct device *dev, enum i2s_dir i2s_dir) +{ + const struct i2s_esp32_cfg *dev_cfg = dev->config; + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream; + void *src = NULL, *dst = NULL; + + if (i2s_dir == I2S_DIR_RX) { + stream = &dev_data->rx; + dst = stream->mem_block; + } else if (i2s_dir == I2S_DIR_TX) { + stream = &dev_data->tx; + src = stream->mem_block; + } else { + LOG_ERR("Invalid DMA direction"); + return -EINVAL; + } + + int err; + + err = dma_reload(stream->dma_dev, stream->dma_channel, (uint32_t)src, (uint32_t)dst, + stream->mem_block_len); + if (err < 0) { + LOG_ERR("Error reloading DMA channel[%d]: %d", (int)stream->dma_channel, err); + return -EIO; + } + + if (i2s_dir == I2S_DIR_RX) { + i2s_ll_rx_set_eof_num(dev_data->hal_cxt.dev, stream->mem_block_len); + } + + err = dma_start(stream->dma_dev, stream->dma_channel); + if (err < 0) { + LOG_ERR("Error starting DMA channel[%d]: %d", (int)stream->dma_channel, err); + return -EIO; + } + + return 0; +} + +static int i2s_esp32_start_dma(const struct device *dev, enum i2s_dir i2s_dir) +{ + const struct i2s_esp32_cfg *dev_cfg = dev->config; + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = NULL; + + if (i2s_dir == I2S_DIR_RX) { + stream = &dev_data->rx; + } else if (i2s_dir == I2S_DIR_TX) { + stream = &dev_data->tx; + } else { + LOG_ERR("Invalid DMA direction"); + return -EINVAL; + } + + struct dma_config dma_cfg = {0}; + struct dma_block_config dma_blk = {0}; + unsigned int key = irq_lock(); + + dma_blk.block_size = stream->mem_block_len; + if (i2s_dir == I2S_DIR_RX) { + dma_blk.dest_address = (uint32_t)stream->mem_block; + dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY; + dma_cfg.dma_callback = i2s_esp32_rx_callback; + } else { + dma_blk.source_address = (uint32_t)stream->mem_block; + dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; + dma_cfg.dma_callback = i2s_esp32_tx_callback; + } + dma_cfg.user_data = (void *)dev; + dma_cfg.dma_slot = dev_cfg->i2s_num == 0 ? ESP_GDMA_TRIG_PERIPH_I2S0 : + ESP_GDMA_TRIG_PERIPH_I2S1; + dma_cfg.block_count = 1; + dma_cfg.head_block = &dma_blk; + + int err, ret = 0; + + err = dma_config(stream->dma_dev, stream->dma_channel, &dma_cfg); + if (err < 0) { + LOG_ERR("Error configuring DMA channel[%d]: %d", (int)stream->dma_channel, err); + ret = -EINVAL; + goto unlock; + } + + if (i2s_dir == I2S_DIR_RX) { + i2s_ll_rx_set_eof_num(dev_data->hal_cxt.dev, stream->mem_block_len); + } + + err = dma_start(stream->dma_dev, stream->dma_channel); + if (err < 0) { + LOG_ERR("Error starting DMA channel[%d]: %d", (int)stream->dma_channel, err); + ret = -EIO; + goto unlock; + } + +unlock: + irq_unlock(key); + return ret; +} + +static int i2s_esp32_rx_start_transfer(const struct device *dev) +{ + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = &dev_data->rx; + i2s_hal_context_t *hal_cxt = &dev_data->hal_cxt; + int err; + + err = k_mem_slab_alloc(stream->i2s_cfg.mem_slab, &stream->mem_block, K_NO_WAIT); + if (err < 0) { + return -ENOMEM; + } + stream->mem_block_len = stream->i2s_cfg.block_size; + + i2s_hal_rx_stop(hal_cxt); + i2s_hal_rx_reset(hal_cxt); + i2s_hal_rx_reset_fifo(hal_cxt); + + err = i2s_esp32_start_dma(dev, I2S_DIR_RX); + if (err < 0) { + LOG_ERR("Failed to start RX DMA transfer: %d", err); + return -EIO; + } + + i2s_hal_rx_start(hal_cxt); + + return 0; +} + +static int i2s_esp32_tx_start_transfer(const struct device *dev) +{ + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = &dev_data->tx; + i2s_hal_context_t *hal_cxt = &dev_data->hal_cxt; + int err; + + err = i2s_esp32_queue_get(&stream->queue, &stream->mem_block, &stream->mem_block_len); + if (err < 0) { + return -ENOMEM; + } + k_sem_give(&stream->queue.sem); + + i2s_hal_tx_stop(hal_cxt); + i2s_hal_tx_reset(hal_cxt); + i2s_hal_tx_reset_fifo(hal_cxt); + + err = i2s_esp32_start_dma(dev, I2S_DIR_TX); + if (err < 0) { + LOG_ERR("Failed to start TX DMA transfer: %d", err); + return -EIO; + } + + i2s_hal_tx_start(hal_cxt); + + return 0; +} + +static void i2s_esp32_rx_stop_transfer(const struct device *dev) +{ + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = &dev_data->rx; + i2s_hal_context_t *hal_cxt = &dev_data->hal_cxt; + + i2s_hal_rx_stop(hal_cxt); + dma_stop(stream->dma_dev, stream->dma_channel); + + if (stream->mem_block != NULL) { + k_mem_slab_free(stream->i2s_cfg.mem_slab, stream->mem_block); + stream->mem_block = NULL; + stream->mem_block_len = 0; + } +} + +static void i2s_esp32_tx_stop_transfer(const struct device *dev) +{ + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = &dev_data->tx; + i2s_hal_context_t *hal_cxt = &dev_data->hal_cxt; + + i2s_hal_tx_stop(hal_cxt); + dma_stop(stream->dma_dev, stream->dma_channel); + + if (stream->mem_block != NULL) { + k_mem_slab_free(stream->i2s_cfg.mem_slab, stream->mem_block); + stream->mem_block = NULL; + stream->mem_block_len = 0; + } +} + +static void i2s_esp32_rx_callback(const struct device *dma_dev, void *arg, uint32_t channel, + int status) +{ + const struct device *dev = (const struct device *)arg; + const struct i2s_esp32_cfg *dev_cfg = dev->config; + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = &dev_data->rx; + + if (status < 0) { + stream->state = I2S_STATE_ERROR; + LOG_ERR("RX status bad: %d", status); + goto rx_disable; + } + + if (stream->mem_block == NULL) { + stream->state = I2S_STATE_ERROR; + LOG_ERR("RX mem_block NULL"); + goto rx_disable; + } + + int err; + + err = i2s_esp32_queue_put(&stream->queue, stream->mem_block, stream->mem_block_len); + if (err < 0) { + stream->state = I2S_STATE_ERROR; + goto rx_disable; + } + k_sem_give(&stream->queue.sem); + + if (stream->state == I2S_STATE_STOPPING) { + stream->state = I2S_STATE_READY; + goto rx_disable; + } + + err = k_mem_slab_alloc(stream->i2s_cfg.mem_slab, &stream->mem_block, K_NO_WAIT); + if (err < 0) { + stream->state = I2S_STATE_ERROR; + goto rx_disable; + } + stream->mem_block_len = stream->i2s_cfg.block_size; + + err = i2s_esp32_restart_dma(dev, I2S_DIR_RX); + if (err < 0) { + stream->state = I2S_STATE_ERROR; + LOG_ERR("Failed to restart RX transfer: %d", err); + goto rx_disable; + } + + return; + +rx_disable: + stream->stop_transfer(dev); +} + +static void i2s_esp32_tx_callback(const struct device *dma_dev, void *arg, uint32_t channel, + int status) +{ + const struct device *dev = (const struct device *)arg; + const struct i2s_esp32_cfg *dev_cfg = dev->config; + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream = &dev_data->tx; + void *mem_block_tmp; + size_t mem_block_size; + + if (status < 0) { + stream->state = I2S_STATE_ERROR; + LOG_ERR("TX bad status: %d", status); + goto tx_disable; + } + + if (stream->mem_block == NULL) { + stream->state = I2S_STATE_ERROR; + LOG_ERR("TX mem_block NULL"); + goto tx_disable; + } + + if (stream->state == I2S_STATE_STOPPING) { + if (stream->queue.count == 0) { + stream->queue_drop(stream); + stream->state = I2S_STATE_READY; + goto tx_disable; + } else if (stream->stop_without_draining == true) { + stream->state = I2S_STATE_READY; + goto tx_disable; + } + /*else: DRAIN trigger, so continue until queue is empty*/ + } + + if (stream->last_block) { + stream->state = I2S_STATE_READY; + goto tx_disable; + } + + int err; + + mem_block_tmp = stream->mem_block; + err = i2s_esp32_queue_get(&stream->queue, &stream->mem_block, &stream->mem_block_len); + if (err < 0) { + if (stream->state == I2S_STATE_RUNNING) { + stream->state = I2S_STATE_ERROR; + } else if (stream->state == I2S_STATE_STOPPING) { + stream->state = I2S_STATE_READY; + } else { + stream->state = I2S_STATE_ERROR; + } + goto tx_disable; + } + k_sem_give(&stream->queue.sem); + + err = i2s_esp32_restart_dma(dev, I2S_DIR_TX); + if (err < 0) { + stream->state = I2S_STATE_ERROR; + LOG_ERR("Failed to restart TX transfer: %d", err); + goto tx_disable; + } + + k_mem_slab_free(stream->i2s_cfg.mem_slab, mem_block_tmp); + + return; + +tx_disable: + stream->stop_transfer(dev); +} + +static int i2s_esp32_initialize(const struct device *dev) +{ + const struct i2s_esp32_cfg *dev_cfg = dev->config; + struct i2s_esp32_data *const dev_data = dev->data; + const struct device *clk_dev = dev_cfg->clock_dev; + int err; + + if (!device_is_ready(clk_dev)) { + LOG_ERR("clock control device not ready"); + return -ENODEV; + } + + err = clock_control_on(clk_dev, dev_cfg->clock_subsys); + if (err != 0) { + LOG_ERR("Clock control enabling failed: %d", err); + return -EIO; + } + + i2s_hal_init(&dev_data->hal_cxt, dev_cfg->i2s_num); + i2s_ll_enable_clock(dev_data->hal_cxt.dev); + + err = k_sem_init(&dev_data->rx.queue.sem, 0, CONFIG_I2S_ESP32_RX_BLOCK_COUNT); + if (err != 0) { + return -EINVAL; + } + + err = k_sem_init(&dev_data->tx.queue.sem, CONFIG_I2S_ESP32_TX_BLOCK_COUNT, + CONFIG_I2S_ESP32_TX_BLOCK_COUNT); + if (err != 0) { + return -EINVAL; + } + + if (!device_is_ready(dev_data->tx.dma_dev)) { + LOG_ERR("%s device not ready", dev_data->tx.dma_dev->name); + return -ENODEV; + } + + if (!device_is_ready(dev_data->rx.dma_dev)) { + LOG_ERR("%s device not ready", dev_data->rx.dma_dev->name); + return -ENODEV; + } + + LOG_INF("%s initialized", dev->name); + + return 0; +} + +static int i2s_esp32_configure(const struct device *dev, enum i2s_dir dir, + const struct i2s_config *i2s_cfg) +{ + const struct i2s_esp32_cfg *const dev_cfg = dev->config; + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream; + + switch (dir) { + case I2S_DIR_RX: + stream = &dev_data->rx; + break; + case I2S_DIR_TX: + stream = &dev_data->tx; + break; + case I2S_DIR_BOTH: + LOG_ERR("I2S_DIR_BOTH is not supported"); + return -ENOSYS; + default: + LOG_ERR("Invalid direction"); + return -EINVAL; + } + + if (stream->state != I2S_STATE_NOT_READY && + stream->state != I2S_STATE_READY) { + LOG_ERR("Invalid state: %d", (int)stream->state); + return -EINVAL; + } + + + if (i2s_cfg->frame_clk_freq == 0U) { + stream->queue_drop(stream); + memset(&stream->i2s_cfg, 0, sizeof(struct i2s_config)); + stream->is_slave = false; + stream->state = I2S_STATE_NOT_READY; + return 0; + } + + if (i2s_cfg->word_size != 8 && i2s_cfg->word_size != 16 && + i2s_cfg->word_size != 24 && i2s_cfg->word_size != 32) { + LOG_ERR("Word size not supported: %d", (int)i2s_cfg->word_size); + return -EINVAL; + } + + if (i2s_cfg->channels != 2) { + LOG_ERR("Currently only 2 channels are supported"); + return -EINVAL; + } + + if ((i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) != I2S_FMT_DATA_FORMAT_I2S) { + LOG_ERR("Currently only I2S_FMT_DATA_FORMAT_I2S is supported"); + return -EINVAL; + } + + if (i2s_cfg->options & I2S_OPT_LOOPBACK) { + LOG_ERR("For internal loopback: I2S#_O_SD_GPIO = I2S#_I_SD_GPIO"); + return -EINVAL; + } + + if (i2s_cfg->options & I2S_OPT_PINGPONG) { + LOG_ERR("Unsupported option: I2S_OPT_PINGPONG"); + return -EINVAL; + } + + if ((i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) != 0 && + (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) != 0) { + stream->is_slave = true; + } else if ((i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) == 0 && + (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) == 0) { + stream->is_slave = false; + } else { + LOG_ERR("I2S_OPT_FRAME_CLK option different from I2S_OPT_BIT_CLK option"); + return -EINVAL; + } + + i2s_hal_slot_config_t slot_cfg = {0}; + + slot_cfg.data_bit_width = i2s_cfg->word_size; + slot_cfg.slot_bit_width = I2S_SLOT_BIT_WIDTH_AUTO; + slot_cfg.slot_mode = I2S_SLOT_MODE_STEREO; + slot_cfg.std.slot_mask = I2S_STD_SLOT_BOTH; + slot_cfg.std.ws_width = i2s_cfg->word_size; + slot_cfg.std.ws_pol = i2s_cfg->format & I2S_FMT_FRAME_CLK_INV ? true : false; + slot_cfg.std.bit_shift = true; + slot_cfg.std.left_align = true; + slot_cfg.std.big_endian = false; + slot_cfg.std.bit_order_lsb = i2s_cfg->format & I2S_FMT_DATA_ORDER_LSB ? true : false; + + int err; + uint32_t bit_clk_freq; + i2s_hal_clock_info_t i2s_hal_clock_info; + + err = i2s_esp32_calculate_clock(i2s_cfg, &i2s_hal_clock_info); + if (err != ESP_OK) { + return -EINVAL; + } + + if (dir == I2S_DIR_TX) { + if (dev_data->rx.state != I2S_STATE_NOT_READY) { + if (stream->is_slave && !dev_data->rx.is_slave) { /*full duplex*/ + i2s_ll_share_bck_ws(dev_data->hal_cxt.dev, true); + } else { + i2s_ll_share_bck_ws(dev_data->hal_cxt.dev, false); + } + } else { + i2s_ll_share_bck_ws(dev_data->hal_cxt.dev, false); + } + + i2s_hal_std_set_tx_slot(&dev_data->hal_cxt, stream->is_slave, &slot_cfg); + + i2s_hal_set_tx_clock(&dev_data->hal_cxt, &i2s_hal_clock_info, IS2_ESP32_CLK_SRC); + + err = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (err < 0) { + LOG_ERR("Pins setup failed: %d", err); + return -EIO; + } + + if (dev_data->tx.state != I2S_STATE_NOT_READY) { + if (stream->is_slave && dev_data->rx.is_slave) { + i2s_ll_mclk_bind_to_tx_clk(dev_data->hal_cxt.dev); + } + } + + i2s_hal_std_enable_tx_channel(&dev_data->hal_cxt); + } else if (dir == I2S_DIR_RX) { + if (dev_data->tx.state != I2S_STATE_NOT_READY) { + if (stream->is_slave && !dev_data->tx.is_slave) { /*full duplex*/ + i2s_ll_share_bck_ws(dev_data->hal_cxt.dev, true); + } else { + i2s_ll_share_bck_ws(dev_data->hal_cxt.dev, false); + } + } else { + i2s_ll_share_bck_ws(dev_data->hal_cxt.dev, false); + } + + i2s_hal_std_set_rx_slot(&dev_data->hal_cxt, stream->is_slave, &slot_cfg); + + i2s_hal_set_rx_clock(&dev_data->hal_cxt, &i2s_hal_clock_info, IS2_ESP32_CLK_SRC); + + err = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (err < 0) { + LOG_ERR("Pins setup failed: %d", err); + return -EIO; + } + + if (dev_data->tx.state != I2S_STATE_NOT_READY) { + if (!stream->is_slave && !dev_data->tx.is_slave) { + i2s_ll_mclk_bind_to_rx_clk(dev_data->hal_cxt.dev); + } + } + + i2s_hal_std_enable_rx_channel(&dev_data->hal_cxt); + } + memcpy(&stream->i2s_cfg, i2s_cfg, sizeof(struct i2s_config)); + + stream->state = I2S_STATE_READY; + + return 0; +} + +static const struct i2s_config *i2s_esp32_config_get(const struct device *dev, + enum i2s_dir dir) +{ + struct i2s_esp32_data *dev_data = dev->data; + struct i2s_esp32_stream *stream; + + if (dir == I2S_DIR_RX) { + stream = &dev_data->rx; + } else { + stream = &dev_data->tx; + } + + if (stream->state == I2S_STATE_NOT_READY) { + return NULL; + } + + return &stream->i2s_cfg; +} + +static int i2s_esp32_trigger(const struct device *dev, enum i2s_dir dir, enum i2s_trigger_cmd cmd) +{ + struct i2s_esp32_data *const dev_data = dev->data; + struct i2s_esp32_stream *stream; + unsigned int key; + int err; + + switch (dir) { + case I2S_DIR_RX: + stream = &dev_data->rx; + break; + case I2S_DIR_TX: + stream = &dev_data->tx; + break; + case I2S_DIR_BOTH: + LOG_ERR("Unsupported direction: %d", (int)dir); + return -ENOSYS; + default: + LOG_ERR("Invalid direction: %d", (int)dir); + return -EINVAL; + } + + struct dma_status dma_status; + + switch (cmd) { + case I2S_TRIGGER_START: + if (stream->state != I2S_STATE_READY) { + LOG_ERR("START - Invalid state: %d", (int)stream->state); + return -EIO; + } + + err = stream->start_transfer(dev); + if (err < 0) { + LOG_ERR("START - Transfer start failed: %d", err); + return -EIO; + } + stream->last_block = false; + stream->state = I2S_STATE_RUNNING; + break; + + case I2S_TRIGGER_STOP: + key = irq_lock(); + if (stream->state != I2S_STATE_RUNNING) { + irq_unlock(key); + LOG_ERR("STOP - Invalid state: %d", (int)stream->state); + return -EIO; + } + + err = dma_get_status(stream->dma_dev, stream->dma_channel, &dma_status); + if (err < 0) { + irq_unlock(key); + LOG_ERR("Unable to get DMA channel[%d] status: %d", + (int)stream->dma_channel, err); + return -EIO; + } + + if (dma_status.busy) { + stream->stop_without_draining = true; + stream->state = I2S_STATE_STOPPING; + } else { + stream->stop_transfer(dev); + stream->last_block = true; + stream->state = I2S_STATE_READY; + } + + irq_unlock(key); + break; + + case I2S_TRIGGER_DRAIN: + key = irq_lock(); + if (stream->state != I2S_STATE_RUNNING) { + irq_unlock(key); + LOG_ERR("DRAIN - Invalid state: %d", (int)stream->state); + return -EIO; + } + + err = dma_get_status(stream->dma_dev, stream->dma_channel, &dma_status); + if (err < 0) { + irq_unlock(key); + LOG_ERR("Unable to get DMA channel[%d] status: %d", + (int)stream->dma_channel, err); + return -EIO; + } + + if (dir == I2S_DIR_TX) { + if (stream->queue.count > 0 || dma_status.busy) { + stream->stop_without_draining = false; + stream->state = I2S_STATE_STOPPING; + } else { + stream->stop_transfer(dev); + stream->state = I2S_STATE_READY; + } + } else if (dir == I2S_DIR_RX) { + if (dma_status.busy) { + stream->stop_without_draining = true; + stream->state = I2S_STATE_STOPPING; + } else { + stream->stop_transfer(dev); + stream->last_block = true; + stream->state = I2S_STATE_READY; + } + } else { + irq_unlock(key); + LOG_ERR("Invalid direction: %d", (int)dir); + return -EINVAL; + } + + irq_unlock(key); + break; + + case I2S_TRIGGER_DROP: + if (stream->state == I2S_STATE_NOT_READY) { + LOG_ERR("DROP - invalid state: %d", (int)stream->state); + return -EIO; + } + stream->stop_transfer(dev); + stream->queue_drop(stream); + stream->state = I2S_STATE_READY; + break; + + case I2S_TRIGGER_PREPARE: + if (stream->state != I2S_STATE_ERROR) { + LOG_ERR("PREPARE - invalid state: %d", (int)stream->state); + return -EIO; + } + stream->queue_drop(stream); + stream->state = I2S_STATE_READY; + break; + + default: + LOG_ERR("Unsupported trigger command: %d", (int)cmd); + return -EINVAL; + } + + return 0; +} + +static int i2s_esp32_read(const struct device *dev, void **mem_block, size_t *size) +{ + struct i2s_esp32_data *const dev_data = dev->data; + int err; + + if (dev_data->rx.state == I2S_STATE_NOT_READY) { + LOG_ERR("RX invalid state: %d", (int)dev_data->rx.state); + return -EIO; + } + + if (dev_data->rx.state != I2S_STATE_ERROR) { + err = k_sem_take(&dev_data->rx.queue.sem, + SYS_TIMEOUT_MS(dev_data->rx.i2s_cfg.timeout)); + if (err < 0) { + LOG_ERR("RX queue empty"); + return err; + } + } + + err = i2s_esp32_queue_get(&dev_data->rx.queue, mem_block, size); + if (err < 0) { + LOG_ERR("RX queue empty"); + return -EIO; + } + + return 0; +} + +static int i2s_esp32_write(const struct device *dev, void *mem_block, size_t size) +{ + struct i2s_esp32_data *const dev_data = dev->data; + int err; + + if (dev_data->tx.state != I2S_STATE_RUNNING && + dev_data->tx.state != I2S_STATE_READY) { + LOG_ERR("TX Invalid state: %d", (int)dev_data->tx.state); + return -EIO; + } + + if (size > dev_data->tx.i2s_cfg.block_size) { + LOG_ERR("Max write size is: %u", (unsigned int)dev_data->tx.i2s_cfg.block_size); + return -EINVAL; + } + + err = k_sem_take(&dev_data->tx.queue.sem, SYS_TIMEOUT_MS(dev_data->tx.i2s_cfg.timeout)); + if (err < 0) { + LOG_ERR("TX queue full"); + return err; + } + (void)i2s_esp32_queue_put(&dev_data->tx.queue, mem_block, size); + + return 0; +} + +static const struct i2s_driver_api i2s_esp32_driver_api = { + .configure = i2s_esp32_configure, + .config_get = i2s_esp32_config_get, + .trigger = i2s_esp32_trigger, + .read = i2s_esp32_read, + .write = i2s_esp32_write, +}; + +#define I2S(idx) DT_NODELABEL(i2s##idx) + +#define I2S_ESP32_DMA_CHANNEL_INIT(index, dir) \ + .dir = { \ + .state = I2S_STATE_NOT_READY, \ + .is_slave = false, \ + .dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)), \ + .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \ + .mem_block = NULL, \ + .mem_block_len = 0, \ + .start_transfer = i2s_esp32_##dir##_start_transfer, \ + .stop_transfer = i2s_esp32_##dir##_stop_transfer, \ + .queue_drop = i2s_esp32_##dir##_queue_drop, \ + .queue.array = i2s_esp32_##dir##_##index##_array, \ + .queue.len = ARRAY_SIZE(i2s_esp32_##dir##_##index##_array), \ + .queue.count = 0, \ + .last_block = false, \ + .stop_without_draining = false, \ + } + +#define I2S_ESP32_INIT(index) \ + PINCTRL_DT_INST_DEFINE(index); \ + \ + static const struct i2s_esp32_cfg i2s_esp32_config_##index = { \ + .i2s_num = index, \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ + .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(I2S(index))), \ + .clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(I2S(index), offset), \ + }; \ + \ + static struct queue_item i2s_esp32_rx_##index##_array[CONFIG_I2S_ESP32_RX_BLOCK_COUNT]; \ + static struct queue_item i2s_esp32_tx_##index##_array[CONFIG_I2S_ESP32_TX_BLOCK_COUNT]; \ + \ + static struct i2s_esp32_data i2s_esp32_data_##index = { \ + .hal_cxt = \ + { \ + .dev = (i2s_dev_t *)DT_REG_ADDR(I2S(index)), \ + }, \ + UTIL_AND(DT_INST_DMAS_HAS_NAME(index, rx), \ + I2S_ESP32_DMA_CHANNEL_INIT(index, rx)), \ + UTIL_AND(DT_INST_DMAS_HAS_NAME(index, tx), \ + I2S_ESP32_DMA_CHANNEL_INIT(index, tx)), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(index, &i2s_esp32_initialize, NULL, &i2s_esp32_data_##index, \ + &i2s_esp32_config_##index, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, \ + &i2s_esp32_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(I2S_ESP32_INIT) diff --git a/drivers/i2s/i2s_esp32.h b/drivers/i2s/i2s_esp32.h new file mode 100644 index 000000000000000..9d0c524e5403e8a --- /dev/null +++ b/drivers/i2s/i2s_esp32.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_I2S_I2S_ESP32_H_ +#define ZEPHYR_DRIVERS_I2S_I2S_ESP32_H_ + +#include "esp_types.h" +#include "esp_err.h" +#include "soc/i2s_periph.h" +#include "soc/rtc_periph.h" +#include "hal/i2s_hal.h" + +struct queue_item { + void *buffer; + size_t size; +}; + +/* Minimal ring buffer implementation */ +struct ring_buffer { + struct k_sem sem; + struct queue_item *array; + uint16_t len; + uint16_t count; + uint16_t head; + uint16_t tail; +}; + +struct i2s_esp32_stream { + int32_t state; + struct i2s_config i2s_cfg; + bool is_slave; + + const struct device *dma_dev; + uint32_t dma_channel; + + bool stop_without_draining; + + void *mem_block; + size_t mem_block_len; + bool last_block; + + struct ring_buffer queue; + void (*queue_drop)(struct i2s_esp32_stream *stream); + int (*start_transfer)(const struct device *dev); + void (*stop_transfer)(const struct device *dev); +}; + +/* Device constant configuration parameters */ +struct i2s_esp32_cfg { + const int i2s_num; + const struct pinctrl_dev_config *pcfg; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; +}; + +/* Device run time data */ +struct i2s_esp32_data { + i2s_hal_context_t hal_cxt; + i2s_hal_clock_info_t clk_info; + struct i2s_esp32_stream rx; + struct i2s_esp32_stream tx; +}; + +#endif /* ZEPHYR_DRIVERS_I2S_I2S_ESP32_H_ */ diff --git a/dts/bindings/i2s/espressif,esp32-i2s.yaml b/dts/bindings/i2s/espressif,esp32-i2s.yaml new file mode 100644 index 000000000000000..afd0a991bed5401 --- /dev/null +++ b/dts/bindings/i2s/espressif,esp32-i2s.yaml @@ -0,0 +1,18 @@ +description: ESP32 I2S + +compatible: "espressif,esp32-i2s" + +include: [i2s-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + interrupts: + required: true diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi index 71b703114c36b46..8e5b2a1b7abb070 100644 --- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi +++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi @@ -170,6 +170,17 @@ status = "disabled"; }; + i2s1: i2s@6002d000 { + compatible = "espressif,esp32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6002d000 0x1000>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&rtc ESP32_I2S1_MODULE>; + status = "disabled"; + }; + uart0: uart@60000000 { compatible = "espressif,esp32-uart"; reg = <0x60000000 0x400>; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index 2b571a659608760..55cf313482a7256 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -267,6 +267,28 @@ status = "disabled"; }; + i2s0: i2s@6000f000 { + compatible = "espressif,esp32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6000f000 0x1000>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&rtc ESP32_I2S0_MODULE>; + status = "disabled"; + }; + + i2s1: i2s@6002d000 { + compatible = "espressif,esp32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6002d000 0x1000>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&rtc ESP32_I2S1_MODULE>; + status = "disabled"; + }; + spi2: spi@60024000 { compatible = "espressif,esp32-spi"; reg = <0x60024000 DT_SIZE_K(4)>; diff --git a/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h index 2eda20f9cb36045..dfd8155bbad3f56 100644 --- a/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h @@ -143,6 +143,475 @@ #define I2C0_SDA_GPIO21 \ ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +/* I2S1_I_BCK */ +#define I2S1_I_BCK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S1_I_BCK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +/* I2S1_I_SD */ +#define I2S1_I_SD_GPIO0 \ + ESP32_PINMUX(0, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO1 \ + ESP32_PINMUX(1, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO2 \ + ESP32_PINMUX(2, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO3 \ + ESP32_PINMUX(3, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO4 \ + ESP32_PINMUX(4, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO5 \ + ESP32_PINMUX(5, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO6 \ + ESP32_PINMUX(6, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO7 \ + ESP32_PINMUX(7, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO8 \ + ESP32_PINMUX(8, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO9 \ + ESP32_PINMUX(9, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO10 \ + ESP32_PINMUX(10, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO11 \ + ESP32_PINMUX(11, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO12 \ + ESP32_PINMUX(12, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO13 \ + ESP32_PINMUX(13, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO14 \ + ESP32_PINMUX(14, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO15 \ + ESP32_PINMUX(15, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO16 \ + ESP32_PINMUX(16, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO17 \ + ESP32_PINMUX(17, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO18 \ + ESP32_PINMUX(18, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO19 \ + ESP32_PINMUX(19, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO20 \ + ESP32_PINMUX(20, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO21 \ + ESP32_PINMUX(21, ESP_I2SI_SD_IN, ESP_NOSIG) + +/* I2S1_I_WS */ +#define I2S1_I_WS_GPIO0 \ + ESP32_PINMUX(0, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO1 \ + ESP32_PINMUX(1, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO2 \ + ESP32_PINMUX(2, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO3 \ + ESP32_PINMUX(3, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO4 \ + ESP32_PINMUX(4, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO5 \ + ESP32_PINMUX(5, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO6 \ + ESP32_PINMUX(6, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO7 \ + ESP32_PINMUX(7, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO8 \ + ESP32_PINMUX(8, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO9 \ + ESP32_PINMUX(9, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO10 \ + ESP32_PINMUX(10, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO11 \ + ESP32_PINMUX(11, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO12 \ + ESP32_PINMUX(12, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO13 \ + ESP32_PINMUX(13, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO14 \ + ESP32_PINMUX(14, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO15 \ + ESP32_PINMUX(15, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO16 \ + ESP32_PINMUX(16, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO17 \ + ESP32_PINMUX(17, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO18 \ + ESP32_PINMUX(18, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO19 \ + ESP32_PINMUX(19, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO20 \ + ESP32_PINMUX(20, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S1_I_WS_GPIO21 \ + ESP32_PINMUX(21, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +/* I2S1_MCLK */ +#define I2S1_MCLK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S1_MCLK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +/* I2S1_O_BCK */ +#define I2S1_O_BCK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S1_O_BCK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +/* I2S1_O_SD */ +#define I2S1_O_SD_GPIO0 \ + ESP32_PINMUX(0, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO1 \ + ESP32_PINMUX(1, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO2 \ + ESP32_PINMUX(2, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO3 \ + ESP32_PINMUX(3, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO4 \ + ESP32_PINMUX(4, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO5 \ + ESP32_PINMUX(5, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO6 \ + ESP32_PINMUX(6, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO7 \ + ESP32_PINMUX(7, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO8 \ + ESP32_PINMUX(8, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO9 \ + ESP32_PINMUX(9, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO10 \ + ESP32_PINMUX(10, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO11 \ + ESP32_PINMUX(11, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO12 \ + ESP32_PINMUX(12, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO13 \ + ESP32_PINMUX(13, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO14 \ + ESP32_PINMUX(14, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO15 \ + ESP32_PINMUX(15, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO16 \ + ESP32_PINMUX(16, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO17 \ + ESP32_PINMUX(17, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO18 \ + ESP32_PINMUX(18, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO19 \ + ESP32_PINMUX(19, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO20 \ + ESP32_PINMUX(20, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S1_O_SD_GPIO21 \ + ESP32_PINMUX(21, ESP_NOSIG, ESP_I2SO_SD_OUT) + +/* I2S1_O_WS */ +#define I2S1_O_WS_GPIO0 \ + ESP32_PINMUX(0, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO1 \ + ESP32_PINMUX(1, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO2 \ + ESP32_PINMUX(2, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO3 \ + ESP32_PINMUX(3, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO4 \ + ESP32_PINMUX(4, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO5 \ + ESP32_PINMUX(5, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO6 \ + ESP32_PINMUX(6, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO7 \ + ESP32_PINMUX(7, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO8 \ + ESP32_PINMUX(8, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO9 \ + ESP32_PINMUX(9, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO10 \ + ESP32_PINMUX(10, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO11 \ + ESP32_PINMUX(11, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO12 \ + ESP32_PINMUX(12, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO13 \ + ESP32_PINMUX(13, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO14 \ + ESP32_PINMUX(14, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO15 \ + ESP32_PINMUX(15, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO16 \ + ESP32_PINMUX(16, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO17 \ + ESP32_PINMUX(17, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO18 \ + ESP32_PINMUX(18, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO19 \ + ESP32_PINMUX(19, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO20 \ + ESP32_PINMUX(20, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S1_O_WS_GPIO21 \ + ESP32_PINMUX(21, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + /* LEDC_CH0 */ #define LEDC_CH0_GPIO0 \ ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h index f8713bec265902e..045ebda2848fc03 100644 --- a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h @@ -553,6 +553,1910 @@ #define I2C1_SDA_GPIO48 \ ESP32_PINMUX(48, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +/* I2S0_I_BCK */ +#define I2S0_I_BCK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +/* I2S0_I_SD */ +#define I2S0_I_SD_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S0I_SD_IN, ESP_NOSIG) + +/* I2S0_I_WS */ +#define I2S0_I_WS_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +/* I2S0_MCLK */ +#define I2S0_MCLK_GPIO0 \ + ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO1 \ + ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO2 \ + ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO3 \ + ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO4 \ + ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO5 \ + ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO6 \ + ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO7 \ + ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO8 \ + ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO9 \ + ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO10 \ + ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO11 \ + ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO12 \ + ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO13 \ + ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO14 \ + ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO15 \ + ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO16 \ + ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO17 \ + ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO18 \ + ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO19 \ + ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO20 \ + ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO21 \ + ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO26 \ + ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO27 \ + ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO28 \ + ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO29 \ + ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO30 \ + ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO31 \ + ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO32 \ + ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO33 \ + ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO34 \ + ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO35 \ + ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO36 \ + ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO37 \ + ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO38 \ + ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO39 \ + ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO40 \ + ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO41 \ + ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO42 \ + ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO43 \ + ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO44 \ + ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO45 \ + ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO46 \ + ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO47 \ + ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO48 \ + ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +/* I2S0_O_BCK */ +#define I2S0_O_BCK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +/* I2S0_O_SD */ +#define I2S0_O_SD_GPIO0 \ + ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO1 \ + ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO2 \ + ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO3 \ + ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO4 \ + ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO5 \ + ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO6 \ + ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO7 \ + ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO8 \ + ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO9 \ + ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO10 \ + ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO11 \ + ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO12 \ + ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO13 \ + ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO14 \ + ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO15 \ + ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO16 \ + ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO17 \ + ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO18 \ + ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO19 \ + ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO20 \ + ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO21 \ + ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO26 \ + ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO27 \ + ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO28 \ + ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO29 \ + ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO30 \ + ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO31 \ + ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO32 \ + ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO33 \ + ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO34 \ + ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO35 \ + ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO36 \ + ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO37 \ + ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO38 \ + ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO39 \ + ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO40 \ + ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO41 \ + ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO42 \ + ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO43 \ + ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO44 \ + ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO45 \ + ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO46 \ + ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO47 \ + ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO48 \ + ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +/* I2S0_O_WS */ +#define I2S0_O_WS_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +/* I2S1_I_BCK */ +#define I2S1_I_BCK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +/* I2S1_I_SD */ +#define I2S1_I_SD_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S1I_SD_IN, ESP_NOSIG) + +/* I2S1_I_WS */ +#define I2S1_I_WS_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +/* I2S1_MCLK */ +#define I2S1_MCLK_GPIO0 \ + ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO1 \ + ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO2 \ + ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO3 \ + ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO4 \ + ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO5 \ + ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO6 \ + ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO7 \ + ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO8 \ + ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO9 \ + ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO10 \ + ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO11 \ + ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO12 \ + ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO13 \ + ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO14 \ + ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO15 \ + ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO16 \ + ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO17 \ + ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO18 \ + ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO19 \ + ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO20 \ + ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO21 \ + ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO26 \ + ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO27 \ + ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO28 \ + ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO29 \ + ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO30 \ + ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO31 \ + ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO32 \ + ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO33 \ + ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO34 \ + ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO35 \ + ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO36 \ + ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO37 \ + ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO38 \ + ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO39 \ + ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO40 \ + ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO41 \ + ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO42 \ + ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO43 \ + ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO44 \ + ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO45 \ + ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO46 \ + ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO47 \ + ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO48 \ + ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +/* I2S1_O_BCK */ +#define I2S1_O_BCK_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +/* I2S1_O_SD */ +#define I2S1_O_SD_GPIO0 \ + ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO1 \ + ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO2 \ + ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO3 \ + ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO4 \ + ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO5 \ + ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO6 \ + ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO7 \ + ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO8 \ + ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO9 \ + ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO10 \ + ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO11 \ + ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO12 \ + ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO13 \ + ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO14 \ + ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO15 \ + ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO16 \ + ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO17 \ + ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO18 \ + ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO19 \ + ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO20 \ + ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO21 \ + ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO26 \ + ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO27 \ + ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO28 \ + ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO29 \ + ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO30 \ + ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO31 \ + ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO32 \ + ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO33 \ + ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO34 \ + ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO35 \ + ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO36 \ + ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO37 \ + ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO38 \ + ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO39 \ + ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO40 \ + ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO41 \ + ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO42 \ + ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO43 \ + ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO44 \ + ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO45 \ + ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO46 \ + ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO47 \ + ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO48 \ + ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +/* I2S1_O_WS */ +#define I2S1_O_WS_GPIO0 \ + ESP32_PINMUX(0, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO1 \ + ESP32_PINMUX(1, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO2 \ + ESP32_PINMUX(2, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO3 \ + ESP32_PINMUX(3, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO4 \ + ESP32_PINMUX(4, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO5 \ + ESP32_PINMUX(5, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO6 \ + ESP32_PINMUX(6, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO7 \ + ESP32_PINMUX(7, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO8 \ + ESP32_PINMUX(8, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO9 \ + ESP32_PINMUX(9, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO10 \ + ESP32_PINMUX(10, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO11 \ + ESP32_PINMUX(11, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO12 \ + ESP32_PINMUX(12, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO13 \ + ESP32_PINMUX(13, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO14 \ + ESP32_PINMUX(14, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO15 \ + ESP32_PINMUX(15, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO16 \ + ESP32_PINMUX(16, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO17 \ + ESP32_PINMUX(17, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO18 \ + ESP32_PINMUX(18, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO19 \ + ESP32_PINMUX(19, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO20 \ + ESP32_PINMUX(20, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO21 \ + ESP32_PINMUX(21, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO26 \ + ESP32_PINMUX(26, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO27 \ + ESP32_PINMUX(27, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO28 \ + ESP32_PINMUX(28, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO29 \ + ESP32_PINMUX(29, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO30 \ + ESP32_PINMUX(30, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO31 \ + ESP32_PINMUX(31, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO32 \ + ESP32_PINMUX(32, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO33 \ + ESP32_PINMUX(33, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO34 \ + ESP32_PINMUX(34, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO35 \ + ESP32_PINMUX(35, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO36 \ + ESP32_PINMUX(36, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO37 \ + ESP32_PINMUX(37, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO38 \ + ESP32_PINMUX(38, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO39 \ + ESP32_PINMUX(39, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO40 \ + ESP32_PINMUX(40, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO41 \ + ESP32_PINMUX(41, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO42 \ + ESP32_PINMUX(42, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO43 \ + ESP32_PINMUX(43, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO44 \ + ESP32_PINMUX(44, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO45 \ + ESP32_PINMUX(45, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO46 \ + ESP32_PINMUX(46, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO47 \ + ESP32_PINMUX(47, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO48 \ + ESP32_PINMUX(48, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + /* LEDC_CH0 */ #define LEDC_CH0_GPIO0 \ ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) diff --git a/west.yml b/west.yml index d88f0a8911d43f3..e9b8cd867a1295e 100644 --- a/west.yml +++ b/west.yml @@ -157,7 +157,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 826077a9d9c762ea7033f137b992b1b36b4aeacb + revision: pull/282/head path: modules/hal/espressif west-commands: west/west-commands.yml groups: