From b71ee0fd137720ab1c70719b746ce52da3bd7f5d Mon Sep 17 00:00:00 2001
From: Jimmy Zheng <jimmyzhe@andestech.com>
Date: Wed, 28 Jun 2023 14:45:49 +0800
Subject: [PATCH] tests: kernel: gen_isr_table.riscv_direct: exclude
 adp_xc7k_ae350

Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored
mode from csr $mtvec.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
---
 tests/kernel/gen_isr_table/testcase.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/kernel/gen_isr_table/testcase.yaml
index 63735a6993f62fe..28da46e7db09f65 100644
--- a/tests/kernel/gen_isr_table/testcase.yaml
+++ b/tests/kernel/gen_isr_table/testcase.yaml
@@ -50,7 +50,9 @@ tests:
     arch_allow:
       - riscv32
       - riscv64
-    platform_exclude: m2gl025_miv
+    platform_exclude:
+      - m2gl025_miv
+      - adp_xc7k_ae350
     filter: CONFIG_SOC_FAMILY_RISCV_PRIVILEGED
     extra_configs:
       - CONFIG_GEN_IRQ_VECTOR_TABLE=y