From affb7d4a4b9778563419d0eb26d4eac6c4bb0b27 Mon Sep 17 00:00:00 2001 From: Sumit Batra Date: Wed, 31 May 2023 11:33:15 +0530 Subject: [PATCH] board: MIMXRT1062-FMURT6: Fix the sequence of Enet2 ref clk enablement This patch sets ENET2 ref clock to be generated by External OSC ENET2 ref clock direction as output ENET2 ref clk frequency to 50MHz Signed-off-by: Sumit Batra --- drivers/ethernet/eth_mcux.c | 6 ++++++ soc/arm/nxp_imx/rt/soc_rt10xx.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c index 637e4c72260c1e5..774771f41f63d24 100644 --- a/drivers/ethernet/eth_mcux.c +++ b/drivers/ethernet/eth_mcux.c @@ -1059,6 +1059,12 @@ static void eth_mcux_init(const struct device *dev) kENET_RxAccelProtoCheckEnabled; } + /* Set ENET2 ref clock to be generated by External OSC,*/ + /* direction as output and frequency to 50MHz */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) + IOMUXC_GPR->GPR1 |= (IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK); +#endif ENET_Init(context->base, &context->enet_handle, &enet_config, diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c index 754534e67759f91..d22379fd8a79695 100644 --- a/soc/arm/nxp_imx/rt/soc_rt10xx.c +++ b/soc/arm/nxp_imx/rt/soc_rt10xx.c @@ -66,7 +66,12 @@ const clock_enet_pll_config_t ethPllConfig = { #else .enableClkOutput25M = false, #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) .loopDivider = 1, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) + .loopDivider1 = 1, +#endif }; #endif