diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
index 30faa6b200768c2..2fdd36caa95c37d 100644
--- a/drivers/adc/adc_stm32.c
+++ b/drivers/adc/adc_stm32.c
@@ -1756,29 +1756,29 @@ static const struct adc_driver_api api_stm32_driver_api = {
 
 #if defined(CONFIG_ADC_STM32_DMA)
 
-#define ADC_DMA_CHANNEL_INIT(index, src_dev, dest_dev)					\
-	.dma = {									\
-		.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(index, 0)),		\
-		.channel = DT_INST_DMAS_CELL_BY_IDX(index, 0, channel),			\
-		.dma_cfg = {								\
-			.dma_slot = STM32_DMA_SLOT_BY_IDX(index, 0, slot),		\
-			.channel_direction = STM32_DMA_CONFIG_DIRECTION(		\
-				STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),		\
-			.source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE(	\
-				STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),		\
-			.dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE(	\
-				STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),		\
-			.source_burst_length = 1,       /* SINGLE transfer */		\
-			.dest_burst_length = 1,         /* SINGLE transfer */		\
-			.channel_priority = STM32_DMA_CONFIG_PRIORITY(			\
-				STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),		\
-			.dma_callback = dma_callback,					\
-			.block_count = 2,						\
-		},									\
-		.src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC(		\
-			STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),			\
-		.dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC(		\
-			STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),			\
+#define ADC_DMA_CHANNEL_INIT(index, src_dev, dest_dev)                                             \
+	.dma = {                                                                                   \
+		.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(index, 0)),                      \
+		.channel = DT_INST_DMAS_CELL_BY_IDX(index, 0, channel),                            \
+		.dma_cfg = {                                                                       \
+				.dma_slot = STM32_DMA_SLOT_BY_IDX(index, 0, slot),                 \
+				.channel_direction = STM32_DMA_CONFIG_DIRECTION(                   \
+					STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),                \
+				.source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE(        \
+					STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),                \
+				.dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE(         \
+					STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),                \
+				.source_burst_length = 1, /* SINGLE transfer */                    \
+				.dest_burst_length = 1,   /* SINGLE transfer */                    \
+				.channel_priority = STM32_DMA_CONFIG_PRIORITY(                     \
+					STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),                \
+				.dma_callback = dma_callback,                                      \
+				.block_count = 2,                                                  \
+			},                                                                         \
+		.src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC(                       \
+			STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),                                \
+		.dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC(                      \
+			STM32_DMA_CHANNEL_CONFIG_BY_IDX(index, 0)),                                \
 	}
 
 #define ADC_STM32_IRQ_FUNC(index)					\
@@ -1894,42 +1894,37 @@ DT_INST_FOREACH_STATUS_OKAY(GENERATE_ISR)
 			(ADC_DMA_CHANNEL_INIT(id, src, dest)),				\
 			(/* Required for other adc instances without dma */))
 
-#define ADC_STM32_INIT(index)						\
-ADC_STM32_CHECK_DT_CLOCK(index)                                         \
-									\
-PINCTRL_DT_INST_DEFINE(index);						\
-									\
-static const struct stm32_pclken pclken_##index[] =			\
-				 STM32_DT_INST_CLOCKS(index);		\
-									\
-static const struct adc_stm32_cfg adc_stm32_cfg_##index = {		\
-	.base = (ADC_TypeDef *)DT_INST_REG_ADDR(index),			\
-	ADC_STM32_IRQ_FUNC(index)					\
-	.pclken = pclken_##index,					\
-	.pclk_len = DT_INST_NUM_CLOCKS(index),				\
-	.clk_prescaler = ADC_STM32_DT_PRESC(index),			\
-	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index),			\
-	.sequencer_type = DT_INST_PROP(index, st_adc_sequencer),	\
-	.sampling_time_table = DT_INST_PROP(index, sampling_times),	\
-	.num_sampling_time_common_channels =				\
-		DT_INST_PROP_OR(index, num_sampling_time_common_channels, 0),\
-	.res_table_size = DT_INST_PROP_LEN(index, resolutions),		\
-	.res_table = DT_INST_PROP(index, resolutions),			\
-};									\
-									\
-static struct adc_stm32_data adc_stm32_data_##index = {			\
-	ADC_CONTEXT_INIT_TIMER(adc_stm32_data_##index, ctx),		\
-	ADC_CONTEXT_INIT_LOCK(adc_stm32_data_##index, ctx),		\
-	ADC_CONTEXT_INIT_SYNC(adc_stm32_data_##index, ctx),		\
-	ADC_DMA_CHANNEL(index, PERIPHERAL, MEMORY)			\
-};									\
-									\
-PM_DEVICE_DT_INST_DEFINE(index, adc_stm32_pm_action);			\
-									\
-DEVICE_DT_INST_DEFINE(index,						\
-		    &adc_stm32_init, PM_DEVICE_DT_INST_GET(index),	\
-		    &adc_stm32_data_##index, &adc_stm32_cfg_##index,	\
-		    POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,		\
-		    &api_stm32_driver_api);
+#define ADC_STM32_INIT(index)                                                                      \
+	ADC_STM32_CHECK_DT_CLOCK(index)                                                            \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(index);                                                             \
+                                                                                                   \
+	static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index);           \
+                                                                                                   \
+	static const struct adc_stm32_cfg adc_stm32_cfg_##index = {                                \
+		.base = (ADC_TypeDef *)DT_INST_REG_ADDR(index),                                    \
+		ADC_STM32_IRQ_FUNC(index).pclken = pclken_##index,                                 \
+		.pclk_len = DT_INST_NUM_CLOCKS(index),                                             \
+		.clk_prescaler = ADC_STM32_DT_PRESC(index),                                        \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                                     \
+		.sequencer_type = DT_INST_PROP(index, st_adc_sequencer),                           \
+		.sampling_time_table = DT_INST_PROP(index, sampling_times),                        \
+		.num_sampling_time_common_channels =                                               \
+			DT_INST_PROP_OR(index, num_sampling_time_common_channels, 0),              \
+		.res_table_size = DT_INST_PROP_LEN(index, resolutions),                            \
+		.res_table = DT_INST_PROP(index, resolutions),                                     \
+	};                                                                                         \
+                                                                                                   \
+	static struct adc_stm32_data adc_stm32_data_##index = {                                    \
+		ADC_CONTEXT_INIT_TIMER(adc_stm32_data_##index, ctx),                               \
+		ADC_CONTEXT_INIT_LOCK(adc_stm32_data_##index, ctx),                                \
+		ADC_CONTEXT_INIT_SYNC(adc_stm32_data_##index, ctx),                                \
+		ADC_DMA_CHANNEL(index, PERIPHERAL, MEMORY)};                                       \
+                                                                                                   \
+	PM_DEVICE_DT_INST_DEFINE(index, adc_stm32_pm_action);                                      \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(index, &adc_stm32_init, PM_DEVICE_DT_INST_GET(index),                \
+			      &adc_stm32_data_##index, &adc_stm32_cfg_##index, POST_KERNEL,        \
+			      CONFIG_ADC_INIT_PRIORITY, &api_stm32_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(ADC_STM32_INIT)