From 9f20919603dc24dcda8c0a59c95f4addd117fc98 Mon Sep 17 00:00:00 2001 From: Jean Nanchen Date: Mon, 17 Jun 2024 08:48:20 +0000 Subject: [PATCH] drivers: sensor: maxim: max31865: Fix fault bit clearing Ensures D1 sets and D5, D3, D2 reset, preventing undefined states. Signed-off-by: Jean Nanchen --- drivers/sensor/maxim/max31865/max31865.c | 4 ++++ drivers/sensor/maxim/max31865/max31865.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/sensor/maxim/max31865/max31865.c b/drivers/sensor/maxim/max31865/max31865.c index 9fd2fc0108ccecc..2823912094fa494 100644 --- a/drivers/sensor/maxim/max31865/max31865.c +++ b/drivers/sensor/maxim/max31865/max31865.c @@ -177,15 +177,19 @@ static char *max31865_error_to_string(uint8_t fault_register) static int max31865_fault_register(const struct device *dev) { uint8_t fault_register; + uint8_t saved_fault_bits; max31865_spi_read(dev, (REG_FAULT_STATUS), &fault_register, 1); struct max31865_data *data = dev->data; + saved_fault_bits = data->config_control_bits & FAULT_BITS_CLEAR_MASK; /*Clear fault register */ WRITE_BIT(data->config_control_bits, 1, 1); + data->config_control_bits &= ~FAULT_BITS_CLEAR_MASK; configure_device(dev); LOG_ERR("Fault Register: 0x%02x, %s", fault_register, max31865_error_to_string(fault_register)); WRITE_BIT(data->config_control_bits, 1, 0); + data->config_control_bits |= saved_fault_bits ; return 0; } diff --git a/drivers/sensor/maxim/max31865/max31865.h b/drivers/sensor/maxim/max31865/max31865.h index 9efc3221499f2fd..1b8681bf9f8face 100644 --- a/drivers/sensor/maxim/max31865/max31865.h +++ b/drivers/sensor/maxim/max31865/max31865.h @@ -42,6 +42,9 @@ LOG_MODULE_REGISTER(MAX31865, CONFIG_SENSOR_LOG_LEVEL); #define REG_FAULT_STATUS 0x07 #define WR(reg) ((reg) | 0x80) +/* Bitmask to clear fault status bits D5, D3, and D2 */ +#define FAULT_BITS_CLEAR_MASK 0x2C + /** * RTD data, RTD current, and measurement reference * voltage. The ITS-90 standard is used; other RTDs