diff --git a/drivers/power_domain/power_domain_intel_adsp.c b/drivers/power_domain/power_domain_intel_adsp.c
index 47828d6c744e6d..9fa66e5ab967e2 100644
--- a/drivers/power_domain/power_domain_intel_adsp.c
+++ b/drivers/power_domain/power_domain_intel_adsp.c
@@ -9,6 +9,10 @@
 #include <zephyr/pm/device_runtime.h>
 #include <adsp_shim.h>
 
+#if CONFIG_ACE_VERSION_1_5
+#include <adsp_power.h>
+#endif /* CONFIG_ACE_VERSION_1_5 */
+
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);
 
@@ -31,6 +35,17 @@ static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enabl
 			return -1;
 		}
 	} else {
+#if CONFIG_ACE_VERSION_1_5
+		extern uint32_t g_key_read_holder;
+
+		if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) {
+			volatile uint32_t *key_read_ptr = z_soc_uncached_ptr(&g_key_read_holder);
+			uint32_t key_value = *key_read_ptr;
+
+			if (key_value != INTEL_ADSP_ACE15_MAGIC_KEY)
+				return -1;
+		}
+#endif
 		sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) & ~(SPA_bit_mask),
 			    (mem_addr_t)&ACE_DfPMCCU.dfpwrctl);
 	}
diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
index 594fc414bbc734..4da0e07508c1a6 100644
--- a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
+++ b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
@@ -98,4 +98,8 @@ static ALWAYS_INLINE bool soc_cpu_is_powered(int cpu_num)
  */
 #define INTEL_ADSP_HST_DOMAIN_DEV DEVICE_DT_GET(INTEL_ADSP_HST_DOMAIN_DTNODE)
 
+#define INTEL_ADSP_HST_DOMAIN_BIT DT_PROP(INTEL_ADSP_HST_DOMAIN_DTNODE, bit_position)
+
+#define INTEL_ADSP_ACE15_MAGIC_KEY 0xFFFACE15
+
 #endif /* ZEPHYR_SOC_INTEL_ADSP_POWER_H_ */
diff --git a/soc/xtensa/intel_adsp/ace/multiprocessing.c b/soc/xtensa/intel_adsp/ace/multiprocessing.c
index 08a0aab16c4685..fbdc146c6c73e6 100644
--- a/soc/xtensa/intel_adsp/ace/multiprocessing.c
+++ b/soc/xtensa/intel_adsp/ace/multiprocessing.c
@@ -26,6 +26,11 @@
 
 #define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))
 
+#if CONFIG_ACE_VERSION_1_5
+__aligned(CONFIG_DCACHE_LINE_SIZE) uint32_t g_key_read_holder;
+__aligned(CONFIG_DCACHE_LINE_SIZE) unsigned int alignment_dummy[0];
+#endif /* CONFIG_ACE_VERSION_1_5 */
+
 static void ipc_isr(void *arg)
 {
 	uint32_t cpu_id = arch_proc_id();
@@ -87,6 +92,10 @@ void soc_mp_init(void)
 
 	/* Set the core 0 active */
 	soc_cpus_active[0] = true;
+#if CONFIG_ACE_VERSION_1_5
+	g_key_read_holder = INTEL_ADSP_ACE15_MAGIC_KEY;
+	sys_cache_data_flush_range(&g_key_read_holder, sizeof(g_key_read_holder));
+#endif /* CONFIG_ACE_VERSION_1_5 */
 }
 
 #ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE