diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index 67c3989fe323d3f..585e4aa8d7faea9 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -8,5 +8,5 @@ config BOARD_INTEL_ADSP select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM - select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL - select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL_SIM + select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL + select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index 5eadeb4fe1a437e..f85ef320fdb705e 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -11,6 +11,6 @@ boards: - name: ace20_lnl variants: - name: 'sim' - - name: ace30_ptl + - name: ace30 variants: - - name: 'sim' + - name: 'ptl' diff --git a/boards/intel/adsp/intel_adsp_ace30_defconfig b/boards/intel/adsp/intel_adsp_ace30_defconfig new file mode 100644 index 000000000000000..913d2a8c3e3a90e --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml index bdfe837bd082fb7..061ac9cd7420425 100644 --- a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml +++ b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp/ace30_ptl +identifier: intel_adsp/ace30/ptl name: ACE 3.0 Panther Lake Audio DSP type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml deleted file mode 100644 index 3bf48d4c38356b8..000000000000000 --- a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml +++ /dev/null @@ -1,12 +0,0 @@ -identifier: intel_adsp/ace30_ptl/sim -name: ACE 3.0 Panther Lake Audio DSP -type: sim -simulation: custom -arch: xtensa -toolchain: - - xt-clang -testing: - timeout_multiplier: 8 - ignore_tags: - - net - - bluetooth diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c index b0d44d4da5515bf..b77b4e2db0af5bd 100644 --- a/drivers/dai/intel/dmic/dmic.c +++ b/drivers/dai/intel/dmic/dmic.c @@ -160,7 +160,7 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic) { -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) return dmic->hdamldmic_base; #else return dmic->shim_base; @@ -173,7 +173,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1; uint32_t base = dai_dmic_base(dmic); /* DMIC Change sync period */ -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), base + DMICSYNC_OFFSET); sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, @@ -287,7 +287,7 @@ static void dai_dmic_irq_handler(const void *data) static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic) { /* Disable DMIC clock gating */ -#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL) +#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_ACE30) sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD), dmic->vshim_base + DMICLVSCTL_OFFSET); #else @@ -299,7 +299,7 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic) static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic) { /* Enable DMIC clock gating */ -#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL) +#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_ACE30) sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD), dmic->vshim_base + DMICLVSCTL_OFFSET); #else /* All other CAVS and ACE platforms */ @@ -313,7 +313,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi const struct dai_config *cfg, uint32_t index) { -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) uint16_t pcmsycm = cfg->link_config; uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index; @@ -322,7 +322,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi ARG_UNUSED(dmic); ARG_UNUSED(cfg); ARG_UNUSED(index); -#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) */ +#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) */ } static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) @@ -332,7 +332,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA), base + DMICLCTL_OFFSET); -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) { k_sleep(K_USEC(100)); } diff --git a/drivers/dai/intel/dmic/dmic.h b/drivers/dai/intel/dmic/dmic.h index c507ec1c0eea6fe..760de83b3e675db 100644 --- a/drivers/dai/intel/dmic/dmic.h +++ b/drivers/dai/intel/dmic/dmic.h @@ -173,7 +173,7 @@ struct dai_intel_dmic { /* hardware parameters */ uint32_t reg_base; uint32_t shim_base; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) uint32_t hdamldmic_base; uint32_t vshim_base; #endif diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c index f71b0d47f2ff8c9..d8877f6eca0913e 100644 --- a/drivers/dai/intel/dmic/dmic_nhlt.c +++ b/drivers/dai/intel/dmic/dmic_nhlt.c @@ -282,7 +282,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int c static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source) { uint32_t val; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */ +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) /* ACE 2.0,3.0 */ val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); val &= ~DMICLVSCTL_MLCS; val |= FIELD_PREP(DMICLVSCTL_MLCS, source); @@ -303,7 +303,7 @@ static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic) { uint32_t val; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */ +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) /* ACE 2.0,3.0 */ val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); return FIELD_GET(DMICLVSCTL_MLCS, val); #else diff --git a/drivers/dai/intel/ssp/dai-params-intel-ipc4.h b/drivers/dai/intel/ssp/dai-params-intel-ipc4.h index 6d078cd09411c41..9af572ad36667c2 100644 --- a/drivers/dai/intel/ssp/dai-params-intel-ipc4.h +++ b/drivers/dai/intel/ssp/dai-params-intel-ipc4.h @@ -269,7 +269,7 @@ struct dai_intel_ipc4_ssp_mclk_config_2 { } __packed; struct dai_intel_ipc4_ssp_driver_config { -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config; #else struct dai_intel_ipc4_ssp_config i2s_config; diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c index 58ab0c101708987..8a4a18d8a334a1d 100644 --- a/drivers/dai/intel/ssp/ssp.c +++ b/drivers/dai/intel/ssp/ssp.c @@ -800,7 +800,7 @@ static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t s ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET, I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index), DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE); -#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_ACE30 sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) | I2SLCTL_SPA(ssp_index), dai_hdamlssp_base(dp) + I2SLCTL_OFFSET); @@ -835,7 +835,7 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t I2SLCTL_CPA(ssp_index), 0, DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE); -#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_ACE30 sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)), dai_hdamlssp_base(dp) + I2SLCTL_OFFSET); @@ -873,7 +873,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp, /* Program HDA input stream parameters */ sys_write16((pcmsycm & 0xffff), reg_add); } -#elif defined(CONFIG_SOC_INTEL_ACE30_PTL) +#elif defined(CONFIG_SOC_ACE30) const struct dai_intel_ipc4_ssp_configuration_blob_ver_3_0 *blob30 = spec_config; const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config; uint64_t time_slot_map = 0; @@ -930,7 +930,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp) * SSSR_TNF is cleared when TX FIFO is empty or full, * so wait for set TNF then for TFL zero - order matter. */ -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(dp->tdm_slot_group), SSMODyCS_TNF, SSMODyCS_TNF, DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE); @@ -959,7 +959,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp) } } -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp) { uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX; @@ -1191,7 +1191,7 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp) mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate; #endif -#ifndef CONFIG_SOC_INTEL_ACE30_PTL +#ifndef CONFIG_SOC_ACE30 if (need_ecs) { sscr0 |= SSCR0_ECS; } @@ -1724,7 +1724,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co sys_write32(sspsp2, dai_base(dp) + SSPSP2); sys_write32(ssioc, dai_base(dp) + SSIOC); sys_write32(ssto, dai_base(dp) + SSTO); -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) { sys_write64(sstsa, dai_base(dp) + SSMODyTSA(idx)); } @@ -1777,7 +1777,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co ssp_plat_data->clk_active |= SSP_CLK_BCLK_ES_REQ; if (enable_sse) { -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, SSMIDyCS_RSRE); dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), @@ -1806,7 +1806,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co LOG_INF("hw_free stage: releasing BCLK clocks for SSP%d...", dp->dai_index); if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) { -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) { dai_ssp_update_bits(dp, SSMODyCS(idx), SSMODyCS_TSRE, 0); } @@ -1985,7 +1985,7 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s ~I2CLCTL_MLCS(0x7)) | I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) + I2SLCTL_OFFSET); -#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_ACE30 sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) & ~I2CLCTL_MLCS(0x7)) | I2CLCTL_MLCS(link->clock_source), @@ -2065,7 +2065,7 @@ static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp, return 0; } -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg, const void *spec_config) { @@ -2184,7 +2184,7 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp); int err; -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_ACE30 dp->tdm_slot_group = cfg->tdm_slot_group; #endif @@ -2322,7 +2322,7 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction) /* enable DMA */ -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_ACE30 if (direction == DAI_DIR_PLAYBACK) { dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, SSMODyCS_TSRE); @@ -2392,7 +2392,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction) if (direction == DAI_DIR_CAPTURE && dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING) { LOG_INF("SSP%d RX", dp->dai_index); -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_ACE30 dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RXEN, 0); dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, 0); #else @@ -2407,7 +2407,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction) if (direction == DAI_DIR_PLAYBACK && dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) { LOG_INF("SSP%d TX", dp->dai_index); -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_ACE30 dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, 0); dai_ssp_empty_tx_fifo(dp); dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TXEN, 0); diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h index 560b5d3df5f6e3e..d9779f1fcb701d6 100644 --- a/drivers/dai/intel/ssp/ssp.h +++ b/drivers/dai/intel/ssp/ssp.h @@ -52,7 +52,7 @@ #include "ssp_regs_v1.h" #elif defined(CONFIG_SOC_INTEL_ACE20_LNL) #include "ssp_regs_v2.h" -#elif defined(CONFIG_SOC_INTEL_ACE30_PTL) +#elif defined(CONFIG_SOC_ACE30) #include "ssp_regs_v3.h" #else #error "Missing ssp definitions" @@ -116,7 +116,7 @@ struct dai_intel_ssp_plat_data { uint32_t base; uint32_t ip_base; uint32_t shim_base; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_ACE30) uint32_t hdamlssp_base; uint32_t i2svss_base; #endif diff --git a/drivers/dma/dma_intel_adsp_hda.c b/drivers/dma/dma_intel_adsp_hda.c index 5a2dc1a1e0f5be8..d8a3279f86a52cc 100644 --- a/drivers/dma/dma_intel_adsp_hda.c +++ b/drivers/dma/dma_intel_adsp_hda.c @@ -235,7 +235,7 @@ int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel, stat->pending_length = used; stat->free = unused; -#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_ACE30 /* Linear Link Position via HDA-DMA is only supported on ACE2 or newer */ if (cfg->direction == MEMORY_TO_PERIPHERAL || cfg->direction == PERIPHERAL_TO_MEMORY) { uint32_t tmp; diff --git a/dts/xtensa/intel/intel_adsp_ace30.dtsi b/dts/xtensa/intel/intel_adsp_ace30.dtsi new file mode 100644 index 000000000000000..97be77eb7570b68 --- /dev/null +++ b/dts/xtensa/intel/intel_adsp_ace30.dtsi @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <0>; + cpu-power-states = <&d0i3 &d3>; + i-cache-line-size = <64>; + d-cache-line-size = <64>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <1>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <2>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <3>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <4>; + cpu-power-states = <&d0i3 &d3>; + }; + }; + + power-states { + d0i3: idle { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + min-residency-us = <200>; + exit-latency-us = <100>; + }; + /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. + * The procedure is triggered by IPC from the HOST (SET_DX). + */ + d3: off { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + min-residency-us = <0>; + exit-latency-us = <0>; + status = "disabled"; + }; + }; + + sram0: memory@a0020000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0020000 DT_SIZE_K(4608)>; + }; + + sram0virtual: virtualmemory@a0020000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0020000 DT_SIZE_K(8192)>; + }; + + sram1: memory@a0000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0000000 DT_SIZE_K(64)>; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + clkctl: clkctl { + compatible = "intel,adsp-shim-clkctl"; + adsp-clkctl-clk-wovcro = <0>; + adsp-clkctl-clk-ipll = <1>; + adsp-clkctl-freq-enc = <0xc 0x4>; + adsp-clkctl-freq-mask = <0x0 0x0>; + adsp-clkctl-freq-default = <1>; + adsp-clkctl-freq-lowest = <0>; + wovcro-supported; + }; + + audioclk: audio-clock { + compatible = "fixed-clock"; + clock-frequency = <24576000>; + #clock-cells = <0>; + }; + + pllclk: pll-clock { + compatible = "fixed-clock"; + clock-frequency = <96000000>; + #clock-cells = <0>; + }; + + IMR1: memory@A1000000 { + compatible = "intel,adsp-imr"; + reg = <0xA1000000 DT_SIZE_M(16)>; + block-size = <0x1000>; + zephyr,memory-region = "IMR1"; + }; + + soc { + l1ccap: l1ccap@3fe80080 { + compatible = "intel,adsp-l1ccap"; + reg = <0x3fe80080 0x4>; + }; + + l1ccfg: l1ccfg@3fe80084 { + compatible = "intel,adsp-l1ccfg"; + reg = <0x3fe80084 0x4>; + }; + + l1pcfg: l1pcfg@3fe80088 { + compatible = "intel,adsp-l1pcfg"; + reg = <0x3fe80088 0x4>; + }; + + lsbpm: lsbpm@71d80 { + compatible = "intel,adsp-lsbpm"; + reg = <0x71d80 0x0008>; + }; + + hsbpm: hsbpm@17a800 { + compatible = "intel,adsp-hsbpm"; + reg = <0x17a800 0x0008>; + }; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0x00 0x400>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + hdamlddmic: hdamlddmic@cc0 { + compatible = "intel,adsp-hda-dmic-cap"; + reg = <0xcc0 0x40>; + status = "okay"; + }; + + dmic0: dai-dmic0@10100 { + compatible = "intel,dai-dmic"; + reg = <0x10100 0x8000>; + shim = <0x10000>; + fifo = <0x0008>; + interrupts = <0x08 0 0>; + interrupt-parent = <&ace_intc>; + power-domain = <&hub_ulp_domain>; + }; + + dmic1: dai-dmic1@10100 { + compatible = "intel,dai-dmic"; + reg = <0x10100 0x8000>; + shim = <0x10000>; + fifo = <0x0108>; + interrupts = <0x08 0 0>; + interrupt-parent = <&ace_intc>; + power-domain = <&hub_ulp_domain>; + }; + + dmicvss: dmicvss@16000 { + compatible = "intel,adsp-dmic-vss"; + reg = <0x16000 0x2000>; + status = "okay"; + }; + + sspbase: ssp_base@28000 { + compatible = "intel,ssp-sspbase"; + reg = <0x28000 0x1000>; + }; + + hdamlssp: hdamlssp@d00 { + compatible = "intel,adsp-hda-ssp-cap"; + reg = <0xD00 0x40>; + status = "okay"; + }; + + ssp0: ssp@28100 { + compatible = "intel,ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00028100 0x1000 + 0x00079C00 0x200>; + i2svss = <0x00028C00 0x1000>; + interrupts = <0x00 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 1 + &hda_link_in 1>; + dma-names = "tx", "rx"; + ssp-index = <0>; + power-domain = <&io0_domain>; + status = "okay"; + + ssp00: ssp@0 { + compatible = "intel,ssp-dai"; + reg = <0x0>; + status = "okay"; + }; + + ssp01: ssp@1 { + compatible = "intel,ssp-dai"; + reg = <0x1>; + status = "okay"; + }; + + ssp02: ssp@2 { + compatible = "intel,ssp-dai"; + reg = <0x2>; + status = "okay"; + }; + + ssp03: ssp@3 { + compatible = "intel,ssp-dai"; + reg = <0x3>; + status = "okay"; + }; + + ssp04: ssp@4 { + compatible = "intel,ssp-dai"; + reg = <0x4>; + status = "okay"; + }; + + ssp05: ssp@5 { + compatible = "intel,ssp-dai"; + reg = <0x5>; + status = "okay"; + }; + + ssp06: ssp@6 { + compatible = "intel,ssp-dai"; + reg = <0x6>; + status = "okay"; + }; + + ssp07: ssp@7 { + compatible = "intel,ssp-dai"; + reg = <0x7>; + status = "okay"; + }; + }; + + ssp1: ssp@29100 { + compatible = "intel,ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00029100 0x1000 + 0x00079C00 0x200>; + i2svss = <0x00029C00 0x1000>; + interrupts = <0x01 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 2 + &hda_link_in 2>; + dma-names = "tx", "rx"; + ssp-index = <1>; + power-domain = <&io0_domain>; + status = "okay"; + + ssp10: ssp@10 { + compatible = "intel,ssp-dai"; + reg = <0x10>; + status = "okay"; + }; + + ssp11: ssp@11 { + compatible = "intel,ssp-dai"; + reg = <0x11>; + status = "okay"; + }; + + ssp12: ssp@12 { + compatible = "intel,ssp-dai"; + reg = <0x12>; + status = "okay"; + }; + + ssp13: ssp@13 { + compatible = "intel,ssp-dai"; + reg = <0x13>; + status = "okay"; + }; + + ssp14: ssp@14 { + compatible = "intel,ssp-dai"; + reg = <0x14>; + status = "okay"; + }; + + ssp15: ssp@15 { + compatible = "intel,ssp-dai"; + reg = <0x15>; + status = "okay"; + }; + + ssp16: ssp@16 { + compatible = "intel,ssp-dai"; + reg = <0x16>; + status = "okay"; + }; + + ssp17: ssp@17 { + compatible = "intel,ssp-dai"; + reg = <0x17>; + status = "okay"; + }; + }; + + ssp2: ssp@2a100 { + compatible = "intel,ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0002a100 0x1000 + 0x00079C00 0x200>; + i2svss = <0x0002AC00 0x1000>; + interrupts = <0x02 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 3 + &hda_link_in 3>; + dma-names = "tx", "rx"; + ssp-index = <2>; + power-domain = <&io0_domain>; + status = "okay"; + + ssp20: ssp@20 { + compatible = "intel,ssp-dai"; + reg = <0x20>; + status = "okay"; + }; + + ssp21: ssp@21 { + compatible = "intel,ssp-dai"; + reg = <0x21>; + status = "okay"; + }; + + ssp22: ssp@22 { + compatible = "intel,ssp-dai"; + reg = <0x22>; + status = "okay"; + }; + + ssp23: ssp@23 { + compatible = "intel,ssp-dai"; + reg = <0x23>; + status = "okay"; + }; + + ssp24: ssp@24 { + compatible = "intel,ssp-dai"; + reg = <0x24>; + status = "okay"; + }; + + ssp25: ssp@25 { + compatible = "intel,ssp-dai"; + reg = <0x25>; + status = "okay"; + }; + + ssp26: ssp@26 { + compatible = "intel,ssp-dai"; + reg = <0x26>; + status = "okay"; + }; + + ssp27: ssp@27 { + compatible = "intel,ssp-dai"; + reg = <0x27>; + status = "okay"; + }; + }; + + mem_window0: mem_window@70200 { + compatible = "intel,adsp-mem-window"; + reg = <0x70200 0x8>; + offset = <0x4000>; + memory = <&sram0>; + initialize; + read-only; + }; + + mem_window1: mem_window@70208 { + compatible = "intel,adsp-mem-window"; + reg = <0x70208 0x8>; + memory = <&sram0>; + }; + + mem_window2: mem_window@70210 { + compatible = "intel,adsp-mem-window"; + reg = <0x70210 0x8>; + memory = <&sram0>; + }; + + mem_window3: mem_window@70218 { + compatible = "intel,adsp-mem-window"; + reg = <0x70218 0x8>; + memory = <&sram0>; + read-only; + }; + + adsp_idc: ace_idc@92000 { + compatible = "intel,adsp-idc"; + reg = <0x92000 0x0400>; + interrupts = <24 0 0>; + interrupt-parent = <&ace_intc>; + }; + + dfpmcch: dfpmcch@71ac0 { + compatible = "intel,adsp-dfpmcch"; + reg = <0x00071ac0 0x40>; + }; + + dfpmccu: dfpmccu@71b00 { + compatible = "intel,adsp-dfpmccu"; + reg = <0x71b00 0x100>; + + hub_ulp_domain: hub_ulp_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <15>; + }; + ml0_domain: ml0_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <12>; + }; + io1_domain: io1_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <9>; + }; + io0_domain: io0_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <8>; + }; + hub_hp_domain: hub_hpp_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <6>; + }; + hst_domain: hst_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <5>; + }; + }; + + shim: shim@71f00 { + compatible = "intel,cavs-shim"; + reg = <0x71f00 0x100>; + }; + + tts: tts@72000 { + compatible = "intel,adsp-tts"; + reg = <0x72000 0x70>; + status = "okay"; + }; + + ace_rtc_counter: ace_rtc_counter@72008 { + compatible = "intel,ace-rtc-counter"; + reg = <0x72008 0x0064>; + }; + + ace_timestamp: ace_timestamp@72040 { + compatible = "intel,ace-timestamp"; + reg = <0x72040 0x0032>; + }; + + ace_art_counter: ace_art_counter@72058 { + compatible = "intel,ace-art-counter"; + reg = <0x72058 0x0064>; + }; + + hda_host_out: dma@72800 { + compatible = "intel,adsp-hda-host-out"; + #dma-cells = <1>; + reg = <0x00072800 0x40>; + dma-channels = <9>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&hst_domain>; + interrupts = <13 0 0>; + interrupt-parent = <&ace_intc>; + status = "okay"; + }; + + hda_host_in: dma@72c00 { + compatible = "intel,adsp-hda-host-in"; + #dma-cells = <1>; + reg = <0x00072c00 0x40>; + dma-channels = <11>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&hst_domain>; + interrupts = <12 0 0>; + interrupt-parent = <&ace_intc>; + status = "okay"; + }; + + adsp_host_ipc: ace_host_ipc@73000 { + compatible = "intel,adsp-host-ipc"; + status = "okay"; + reg = <0x73000 0x30>; + interrupts = <0 0 0>; + interrupt-parent = <&ace_intc>; + }; + + hda_link_out: dma@79400 { + compatible = "intel,adsp-hda-link-out"; + #dma-cells = <1>; + reg = <0x00079400 0x40>; + dma-channels = <9>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&io0_domain>; + status = "okay"; + }; + + hda_link_in: dma@79800 { + compatible = "intel,adsp-hda-link-in"; + #dma-cells = <1>; + reg = <0x00079800 0x40>; + dma-channels = <11>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&io0_domain>; + status = "okay"; + }; + + /* This is actually an array of per-core designware + * controllers, but the special setup and extra + * masking layer makes it easier for MTL to handle + * this internally. + */ + ace_intc: ace_intc@94000 { + compatible = "intel,ace-intc"; + reg = <0x94000 0xc00>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <4 0 0>; + num-irqs = <28>; + interrupt-parent = <&core_intc>; + }; + + tlb: tlb@17e000 { + compatible = "intel,adsp-mtl-tlb"; + reg = <0x17e000 0x1000>; + paddr-size = <12>; + exec-bit-idx = <14>; + write-bit-idx= <15>; + }; + + timer: timer { + compatible = "intel,adsp-timer"; + syscon = <&tts>; + }; + }; + + hdas { + #address-cells = <1>; + #size-cells = <0>; + + hda0: hda@0 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0>; + }; + hda1: hda@1 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <1>; + }; + hda2: hda@2 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <2>; + }; + hda3: hda@3 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <3>; + }; + hda4: hda@4 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <4>; + }; + hda5: hda@5 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <5>; + }; + hda6: hda@6 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <6>; + }; + hda7: hda@7 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <7>; + }; + hda8: hda@8 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <8>; + }; + hda9: hda@9 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <9>; + }; + hda10: hda@a { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0a>; + }; + hda11: hda@b { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0b>; + }; + hda12: hda@c { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0c>; + }; + hda13: hda@d { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0d>; + }; + hda14: hda@e { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0e>; + }; + hda15: hda@f { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0f>; + }; + hda16: hda@10 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x10>; + }; + hda17: hda@11 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x11>; + }; + hda18: hda@12 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x12>; + }; + }; +}; diff --git a/soc/intel/intel_adsp/ace/CMakeLists.txt b/soc/intel/intel_adsp/ace/CMakeLists.txt index 0c9c43eb3393c99..a9f189f274931d8 100644 --- a/soc/intel/intel_adsp/ace/CMakeLists.txt +++ b/soc/intel/intel_adsp/ace/CMakeLists.txt @@ -20,7 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) if (CONFIG_XTENSA_MMU) - zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30_PTL mmu_ptl.c) + zephyr_library_sources_ifdef(CONFIG_SOC_ACE30 mmu_ace30.c) endif() set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 similarity index 96% rename from soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl rename to soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 index b5c67ea0f0b85ed..67dfe6dcfafd986 100644 --- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 -if SOC_INTEL_ACE30_PTL +if SOC_ACE30 config MP_MAX_NUM_CPUS default 5 diff --git a/soc/intel/intel_adsp/ace/Kconfig.soc b/soc/intel/intel_adsp/ace/Kconfig.soc index 89ef2eb30dbd5fc..f5578d6fd06dead 100644 --- a/soc/intel/intel_adsp/ace/Kconfig.soc +++ b/soc/intel/intel_adsp/ace/Kconfig.soc @@ -20,7 +20,7 @@ config SOC_INTEL_ACE20_LNL help ACE 2.0 Lunar Lake PCH -config SOC_INTEL_ACE30_PTL +config SOC_ACE30 bool select SOC_SERIES_INTEL_ADSP_ACE help @@ -32,9 +32,9 @@ config SOC_SERIES config SOC_TOOLCHAIN_NAME default "intel_ace15_mtpm" if SOC_INTEL_ACE15_MTPM default "intel_ace15_mtpm" if SOC_INTEL_ACE20_LNL - default "intel_ace30_ptl" if SOC_INTEL_ACE30_PTL + default "intel_ace30" if SOC_ACE30 config SOC default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM default "ace20_lnl" if SOC_INTEL_ACE20_LNL - default "ace30_ptl" if SOC_INTEL_ACE30_PTL + default "ace30" if SOC_ACE30 diff --git a/soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h new file mode 100644 index 000000000000000..585fd8fecb6aad2 --- /dev/null +++ b/soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ +#define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ + +#define DSPCS_REG 0x178d00 + +struct dspcs { + /* + * DSPCSx + * DSP Core Shim + * + * These registers are added by Intel outside of the Tensilica Core for general operation + * control, such as reset, stall, power gating, clock gating etc. + * Note: These registers are accessible through the host space or DSP space depending on + * ownership, as governed by SAI and RS. + */ + struct { + uint32_t cap; + uint32_t ctl; + } capctl[5]; + uint32_t unused0[6]; + + /* + * DSPBRx + * DSP Boot / Recovery + * + * These registers are added by Intel outside of the Tensilica Core for boot / recovery + * control, such as boot path, watch dog timer etc. + */ + struct { + uint32_t brcap; + uint32_t wdtcs; + uint32_t wdtipptr; + uint32_t unused1; + uint32_t bctl; + uint32_t baddr; + uint32_t battr; + uint32_t unused2; + } bootctl[5]; +}; + +#define DSPCS_CTL_SPA BIT(0) +#define DSPCS_CTL_CPA BIT(8) + +#define DSPBR_BCTL_BYPROM BIT(0) +#define DSPBR_BCTL_WAITIPCG BIT(16) +#define DSPBR_BCTL_WAITIPPG BIT(17) + +#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12) +#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13) +#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14) +#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15) +#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16) + +#define DSPBR_WDT_RESUME BIT(8) +#define DSPBR_WDT_RESTART_COMMAND 0x76 + +#define DSPCS (*(volatile struct dspcs *)DSPCS_REG) + +#endif /* ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ */ diff --git a/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h new file mode 100644 index 000000000000000..b34a3fc9f1cc9ba --- /dev/null +++ b/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ +#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ + +/* Low priority interrupt indices */ +#define ACE_INTL_HIPC 0 +#define ACE_INTL_SBIPC 1 +#define ACE_INTL_ML 2 +#define ACE_INTL_IDCA 3 +#define ACE_INTL_LPVML 4 +#define ACE_INTL_SHA 5 +#define ACE_INTL_L1L2M 6 +#define ACE_INTL_I2S 7 +#define ACE_INTL_DMIC 8 +#define ACE_INTL_SNDW 9 +#define ACE_INTL_TTS 10 +#define ACE_INTL_WDT 11 +#define ACE_INTL_HDAHIDMA 12 +#define ACE_INTL_HDAHODMA 13 +#define ACE_INTL_HDALIDMA 14 +#define ACE_INTL_HDALODMA 15 +#define ACE_INTL_I3C 16 +#define ACE_INTL_GPDMA 17 +#define ACE_INTL_PWM 18 +#define ACE_INTL_I2C 19 +#define ACE_INTL_SPI 20 +#define ACE_INTL_UART 21 +#define ACE_INTL_GPIO 22 +#define ACE_INTL_UAOL 23 +#define ACE_INTL_IDCB 24 +#define ACE_INTL_DCW 25 +#define ACE_INTL_DTF 26 +#define ACE_INTL_FLV 27 +#define ACE_INTL_DPDMA 28 + +/* Device interrupt control for the low priority interrupts. It + * provides per-core masking and status checking: ACE_DINT is an array + * of these structs, one per core. The state is in the bottom bits, + * indexed by ACE_INTL_*. Note that some of these use more than one + * bit to discriminate sources (e.g. TTS's bits 0-2 are + * timestamp/comparator0/comparator1). It seems safe to write all 1's + * to the short to "just enable everything", but drivers should + * probably implement proper logic. + * + * Note that this block is independent of the Designware controller + * that manages the shared IRQ. Interrupts need to unmasked in both + * in order to be delivered to software. Per simulator source code, + * this is "upstream" of DW: an interrupt will not be latched into the + * status registers of the DW controller unless the IE bits here are + * set. That seems unlikely to correctly capture the hardware + * behavior (it would mean that the DW controller was being + * independently triggered multiple times by each core!). Beware. + * + * Enable an interrupt for a core with e.g.: + * + * ACE_DINT[core_id].ie[ACE_INTL_TTS] = 0xffff; + */ +struct ace_dint { + uint16_t ie[32]; /* enable */ + uint16_t is[32]; /* status (potentially masked by ie) */ + uint16_t irs[32]; /* "raw" status (hardware input state) */ + uint32_t unused[16]; +}; + +/* This register enables (1) or disable (0) the interrupt of + * each host inter-processor communication capability instance in a single register. + */ +#define DXHIPCIE_REG 0x91040 + +#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG) +#define XTENSA_IRQ_NUM_MASK 0xff +#define XTENSA_IRQ_NUM_SHIFT 0 + +#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) +/* Convert between IRQ_CONNECT() numbers and ACE_INTL_* interrupts */ +#define ACE_IRQ_NUM_SHIFT 8 +#define ACE_IRQ_NUM_MASK 0xFFU +#define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1) + +#define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc)) +#define ACE_IRQ_TO_ZEPHYR(_irq) \ + ((((_irq + 1) & ACE_IRQ_NUM_MASK) << ACE_IRQ_NUM_SHIFT) + ACE_INTC_IRQ) + +#endif diff --git a/soc/intel/intel_adsp/ace/include/ace30/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_ipc_regs.h new file mode 100644 index 000000000000000..74df3245098d789 --- /dev/null +++ b/soc/intel/intel_adsp/ace/include/ace30/adsp_ipc_regs.h @@ -0,0 +1,83 @@ +/* Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H +#define ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H + +#include +#include + +/** + * @file + * + * Inter Processor Communication - used for sending interrupts to and receiving + * them from another device. ACE uses it to talk to the host and the CSME. + * In general there is one of these blocks instantiated for each endpoint of a + * connection. + */ + +/** + * @brief IPC registers layout for Intel ADSP ACE1X SoC family. + */ +struct intel_adsp_ipc { + uint32_t tdr; + uint32_t tda; + uint32_t unused0[2]; + uint32_t idr; + uint32_t ida; + uint32_t unused1[2]; + uint32_t cst; + uint32_t csr; + uint32_t ctl; + uint32_t cap; + uint32_t unused2[52]; + uint32_t tdd; + uint32_t unused3[31]; + uint32_t idd; +}; + +/** + * @brief Set TDA busy bit. + * + * On ACE SoC family boards TDA bit 31 (BUSY) during IPC doorbell acknowledgment + * must be cleared (!), not set (in contrary to CAVS SoC family boards). + * This clears BUSY on the other side of the connection in IDR register. + */ +#define INTEL_ADSP_IPC_ACE1X_TDA_DONE 0 +#define INTEL_ADSP_IPC_BUSY BIT(31) +#define INTEL_ADSP_IPC_DONE BIT(31) + +#define INTEL_ADSP_IPC_CTL_TBIE BIT(0) +#define INTEL_ADSP_IPC_CTL_IDIE BIT(1) +/** + * @brief ACE SoC family Intra DSP Communication. + * + * ACE SoC platform family provides an array of IPC endpoints to be used for + * peer-to-peer communication between DSP cores - master to slave and backwards. + * Given endpoint can be accessed by: + * @code + * IDC[slave_core_id].agents[agent_id].ipc; + * @endcode + */ +struct ace_idc { + /** + * @brief IPC Agent Endpoints. + * + * Each connection is organized into two "agents" ("A" - master core and "B" - slave core). + * Each agent is wired to its own interrupt. + * Agents array represents mutually exclusive IPC endpoint access: + * (A=1/B=0) - agents[0]. + * (A=0/B=1) - agents[1]. + */ + union { + int8_t unused[512]; + struct intel_adsp_ipc ipc; + } agents[2]; +}; + +/** + * @brief Defines register for intra DSP communication. + */ +#define IDC ((volatile struct ace_idc *)INTEL_ADSP_IDC_REG_ADDRESS) + +#endif /* ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H */ diff --git a/soc/intel/intel_adsp/ace/include/ace30/adsp_power.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_power.h new file mode 100644 index 000000000000000..22277dbd64ed3db --- /dev/null +++ b/soc/intel/intel_adsp/ace/include/ace30/adsp_power.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#ifndef ZEPHYR_SOC_INTEL_ADSP_POWER_H_ +#define ZEPHYR_SOC_INTEL_ADSP_POWER_H_ + +/* Value used as delay when waiting for hw register state change. */ +#define HW_STATE_CHECK_DELAY 64 + +/* Power Control register - controls the power domain operations. */ +struct ace_pwrctl { + uint16_t rsvd4 : 5; + uint16_t wphstpg : 1; + uint16_t wphubhppg : 1; + uint16_t wpdspulppg : 1; + uint16_t wpioxpg : 2; + uint16_t rsvd11 : 2; + uint16_t wpmlpg : 1; + uint16_t rsvd14 : 2; + uint16_t phubulppg : 1; +}; + +struct ace_pwrctl2 { + uint16_t wpdsphpxpg : 5; + uint16_t rsvd15 : 11; +}; + +#define ACE_PWRCTL ((volatile struct ace_pwrctl *) &ACE_DfPMCCU.dfpwrctl) +#define ACE_PWRCTL2 ((volatile struct ace_pwrctl2 *) &ACE_DfPMCCU.dfpwrctl2) + +/* Power Status register - reports the power domain status. */ +struct ace_pwrsts { + uint16_t rsvd4 : 5; + uint16_t hstpgs : 1; + uint16_t hubhppgs : 1; + uint16_t dspulppgs : 1; + uint16_t ioxpgs : 2; + uint16_t rsvd11 : 2; + uint16_t mlpgs : 1; + uint16_t rsvd14 : 2; + uint16_t hubulppgs : 1; +}; + +struct ace_pwrsts2 { + uint16_t dsphpxpgs : 5; + uint16_t rsvd15 : 11; +}; + +#define ACE_PWRSTS ((volatile struct ace_pwrsts *) &ACE_DfPMCCU.dfpwrsts) +#define ACE_PWRSTS2 ((volatile struct ace_pwrsts2 *) &ACE_DfPMCCU.dfpwrsts2) + +/** + * @brief Power up a specific CPU. + * + * This sets the "not power gating" bit in the power control + * register to disable power gating to CPU, thus powering up + * the CPU. + * + * @param cpu_num CPU to be powered up. + */ +static ALWAYS_INLINE void soc_cpu_power_up(int cpu_num) +{ + ACE_PWRCTL2->wpdsphpxpg |= BIT(cpu_num); +} + +/** + * @brief Power down a specific CPU. + * + * This clears the "not power gating" bit in the power control + * register to enable power gating to CPU, thus powering down + * the CPU. + * + * @param cpu_num CPU to be powered down. + */ +static ALWAYS_INLINE void soc_cpu_power_down(int cpu_num) +{ + ACE_PWRCTL2->wpdsphpxpg &= ~BIT(cpu_num); +} + +/** + * @brief Test if a CPU is currently powered. + * + * This queries the power status register to see if the CPU + * is currently powered. + * + * @param cpu_num CPU to be queried. + * @return True if CPU is powered, false if now. + */ +static ALWAYS_INLINE bool soc_cpu_is_powered(int cpu_num) +{ + return (ACE_PWRSTS2->dsphpxpgs & BIT(cpu_num)) == BIT(cpu_num); +} + +/** + * @brief Retrieve node identifier for Intel ADSP HOST power domain. + */ +#define INTEL_ADSP_HST_DOMAIN_DTNODE DT_NODELABEL(hst_domain) + +/** + * @brief Intel ADSP HOST power domain pointer. + */ +#define INTEL_ADSP_HST_DOMAIN_DEV DEVICE_DT_GET(INTEL_ADSP_HST_DOMAIN_DTNODE) + +#endif /* ZEPHYR_SOC_INTEL_ADSP_POWER_H_ */ diff --git a/soc/intel/intel_adsp/ace/include/ace30/adsp_shim.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_shim.h new file mode 100644 index 000000000000000..7f4aad745bb7c99 --- /dev/null +++ b/soc/intel/intel_adsp/ace/include/ace30/adsp_shim.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ +#define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ + +#ifndef _ASMLANGUAGE +#include + +/** + * DfPMCCH + * Power Management / Clock Control (HST) Registers + * + * These registers block (HST domain) are for general power management + * and clock control operation for DSP FW. + */ +struct ace_dfpmcch { + uint32_t dfspsreq; /* Offset: 0x00 */ + uint32_t _unused0[3]; + uint32_t dfspsrsp; /* Offset: 0x10 */ + uint32_t _unused1[1]; + uint32_t svcfg; /* Offset: 0x18 */ + uint32_t dfltrc; /* Offset: 0x1c */ + uint32_t _unused2[8]; +}; + +/** + * DfPMCCU + * Power Management / Clock Control (ULP) Registers + * + * These registers block (ULP domain) are for general power management + * and clock control operation for DSP FW. + */ +struct ace_dfpmccu { + uint32_t dfpmccap; /* Offset: 0x00 */ + uint32_t dfhrosccf; /* Offset: 0x04 */ + uint32_t dfxosccf; /* Offset: 0x08 */ + uint32_t dflrosccf; /* Offset: 0x0c */ + uint32_t dfsiorosccf; /* Offset: 0x10 */ + uint32_t dfhsiorosccf; /* Offset: 0x14 */ + uint32_t dfipllrosccf; /* Offset: 0x18 */ + uint32_t dfirosccv; /* Offset: 0x1c */ + uint32_t dffbrcfd; /* Offset: 0x20 */ + uint32_t dfapllptr; /* Offset: 0x24 */ + uint32_t _unused0[20]; + uint32_t dfclkctl; /* Offset: 0x78 */ + uint32_t dfclksts; /* Offset: 0x7c */ + uint32_t dfintclkctl; /* Offset: 0x80 */ + uint32_t dfcrosts; /* Offset: 0x84 */ + uint32_t dfcrodiv; /* Offset: 0x88 */ + uint32_t _unused1[1]; + uint16_t dfpwrctl; /* Offset: 0x90 */ + uint16_t dfpwrsts; /* Offset: 0x92 */ + uint16_t dfpwrctl2; /* Offset: 0x94 */ + uint16_t dfpwrsts2; /* Offset: 0x96 */ + uint32_t dflpsdmas0; /* Offset: 0x98 */ + uint32_t dflpsdmas1; /* Offset: 0x9c */ + uint32_t _unused3[1]; + uint32_t dfldoctl; /* Offset: 0xa4 */ + uint32_t _unused4[2]; + uint32_t dflpsalhsso; /* Offset: 0xb0 */ + uint32_t dflpsalhss1; /* Offset: 0xb4 */ + uint32_t dflpsalhss2; /* Offset: 0xb8 */ + uint32_t dflpsalhss3; /* Offset: 0xbc */ + uint32_t _unused5[10]; +}; + +#define ACE_DfPMCCH (*((volatile struct ace_dfpmcch *)DT_REG_ADDR(DT_NODELABEL(dfpmcch)))) +#define ACE_DfPMCCU (*((volatile struct ace_dfpmccu *)DT_REG_ADDR(DT_NODELABEL(dfpmccu)))) + + +#define ADSP_TTSCAP_OFFSET 0x00 +#define ADSP_RTCWC_OFFSET 0x08 +#define ADSP_DSPWCCTL_OFFSET 0x10 +#define ADSP_DSPWCSTS_OFFSET 0x12 +#define ADSP_DSPWCAV_OFFSET 0x18 +#define ADSP_DSPWC_OFFSET 0x20 +#define ADSP_DSPWCTCS_OFFSET 0x28 +#define ADSP_DSPWCT0C_OFFSET 0x30 +#define ADSP_DSPWCT1C_OFFSET 0x38 +#define ADSP_TSCTRL_OFFSET 0x40 +#define ADSP_ISCS_OFFSET 0x44 +#define ADSP_LSCS_OFFSET 0x48 +#define ADSP_DWCCS_OFFSET 0x50 +#define ADSP_ARTCS_OFFSET 0x58 +#define ADSP_LWCCS_OFFSET 0x60 +#define ADSP_CLTSYNC_OFFSET 0x70 + + + +#define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) + + +#define ADSP_SHIM_TSCTRL_NTK BIT(31) +#define ADSP_SHIM_TSCTRL_IONTE BIT(30) +#define ADSP_SHIM_TSCTRL_DMATS GENMASK(13, 12) +#define ADSP_SHIM_TSCTRL_CLNKS GENMASK(11, 10) +#define ADSP_SHIM_TSCTRL_HHTSE BIT(7) +#define ADSP_SHIM_TSCTRL_LWCS BIT(6) +#define ADSP_SHIM_TSCTRL_ODTS BIT(5) +#define ADSP_SHIM_TSCTRL_CDMAS GENMASK(4, 0) + +#endif /* _ASMLANGUAGE */ + +#define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */ + +#define ACE_CRODIV_CARCDS_MASK GENMASK(7, 0) +#define ACE_CRODIV_CARCDS(x) ((x) & ACE_CRODIV_CARCDS_MASK) + +#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) +#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) + +#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) +#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) + +#define ADSP_DMWBA_ENABLE BIT(0) +#define ADSP_DMWBA_READONLY BIT(1) + +#define ADSP_CLKCTL_OSC_SOURCE_MASK (3<<2) +#define ADSP_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28)) + +/** LDO Control */ +#define ADSP_DSPRA_ADDRESS (0x71A60) +#define ADSP_LPGPDMACxO_ADDRESS(x) (ADSP_DSPRA_ADDRESS + 0x0000 + 0x0002*(x)) +#define ADSP_DSPIOPO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0008) +#define ADSP_GENO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x000C) +#define ADSP_DSPALHO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0010) + + +#define DSP_INIT_IOPO ADSP_DSPIOPO_ADDRESS +#define IOPO_DMIC_FLAG BIT(0) +#define IOPO_DSPKOSEL_FLAG BIT(1) +#define IOPO_ANCOSEL_FLAG BIT(2) +#define IOPO_DMIXOSEL_FLAG BIT(3) +#define IOPO_SLIMOSEL_FLAG BIT(4) +#define IOPO_SNDWOSEL_FLAG BIT(5) +#define IOPO_SLIMDOSEL_FLAG BIT(20) +#define IOPO_I2SSEL_MASK (0x7 << 0x8) + +#define DSP_INIT_GENO ADSP_GENO_ADDRESS +#define GENO_MDIVOSEL BIT(1) +#define GENO_DIOPTOSEL BIT(2) + +#define ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT BIT(1) + +#endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */ diff --git a/soc/intel/intel_adsp/ace/include/ace30/dmic_regs_ace3x.h b/soc/intel/intel_adsp/ace/include/ace30/dmic_regs_ace3x.h new file mode 100644 index 000000000000000..4d02abea74957b9 --- /dev/null +++ b/soc/intel/intel_adsp/ace/include/ace30/dmic_regs_ace3x.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ +#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ + +/* DMIC Link Synchronization */ +#define DMICSYNC_OFFSET 0x1C + +/* Sync Period */ +#define DMICSYNC_SYNCPRD GENMASK(19, 0) + +/* Sync Period Update */ +#define DMICSYNC_SYNCPU BIT(20) + +/* Sync Go */ +#define DMICSYNC_SYNCGO BIT(23) + +/* Command Sync */ +#define DMICSYNC_CMDSYNC BIT(24) + + +/* DMIC Link Control */ +#define DMICLCTL_OFFSET 0x04 + +/* Set Clock Frequency */ +#define DMICLCTL_SCF GENMASK(3, 0) + +/* Offload Enable */ +#define DMICLCTL_OFLEN BIT(4) + +/* Interrupt Enable */ +#define DMICLCTL_INTEN BIT(5) + +/* Set Power Active */ +#define DMICLCTL_SPA BIT(16) + +/* Current Power Active */ +#define DMICLCTL_CPA BIT(23) + +/* Interrupt Status */ +#define DMICLCTL_INTSTS BIT(31) + + +/* Digital Microphone x Link Vendor Specific Control */ +#define DMICLVSCTL_OFFSET 0x04 + +/* Force Clock Gating */ +#define DMICLVSCTL_FCG BIT(26) + +/* Host Link Clock Select */ +#define DMICLVSCTL_MLCS GENMASK(29, 27) + +/* Dynamic Clock Gating Disable */ +#define DMICLVSCTL_DCGD BIT(30) + +/* Idle Clock Gating Disable */ +#define DMICLVSCTL_ICGD BIT(31) + + +/* Digital Microphone PCM Stream y Channel Map + * + * Offset: 12h + 02h * y + */ +#define DMICXPCMSyCM_OFFSET 0x16 +#define DMICXPCMSyCM_SIZE 0x02 + +#endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ */ diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h index 6cc07538da0c7fc..412eb6a4fbf3cbc 100644 --- a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h +++ b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h @@ -6,7 +6,7 @@ #ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ #define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ -#define DSPCS_REG 0x178d00 +#define DSPCS_REG 0x178d00 struct dspcs { /* @@ -43,21 +43,21 @@ struct dspcs { } bootctl[5]; }; -#define DSPCS_CTL_SPA BIT(0) -#define DSPCS_CTL_CPA BIT(8) +#define DSPCS_CTL_SPA BIT(0) +#define DSPCS_CTL_CPA BIT(8) -#define DSPBR_BCTL_BYPROM BIT(0) -#define DSPBR_BCTL_WAITIPCG BIT(16) -#define DSPBR_BCTL_WAITIPPG BIT(17) +#define DSPBR_BCTL_BYPROM BIT(0) +#define DSPBR_BCTL_WAITIPCG BIT(16) +#define DSPBR_BCTL_WAITIPPG BIT(17) -#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12) -#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13) -#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14) -#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15) -#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16) +#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12) +#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13) +#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14) +#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15) +#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16) -#define DSPBR_WDT_RESUME BIT(8) -#define DSPBR_WDT_RESTART_COMMAND 0x76 +#define DSPBR_WDT_RESUME BIT(8) +#define DSPBR_WDT_RESTART_COMMAND 0x76 #define DSPCS (*(volatile struct dspcs *)DSPCS_REG) diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h index bf912746d66b7f5..b34a3fc9f1cc9ba 100644 --- a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h +++ b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h @@ -7,35 +7,35 @@ #define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ /* Low priority interrupt indices */ -#define ACE_INTL_HIPC 0 -#define ACE_INTL_SBIPC 1 -#define ACE_INTL_ML 2 -#define ACE_INTL_IDCA 3 -#define ACE_INTL_LPVML 4 -#define ACE_INTL_SHA 5 -#define ACE_INTL_L1L2M 6 -#define ACE_INTL_I2S 7 -#define ACE_INTL_DMIC 8 -#define ACE_INTL_SNDW 9 -#define ACE_INTL_TTS 10 -#define ACE_INTL_WDT 11 +#define ACE_INTL_HIPC 0 +#define ACE_INTL_SBIPC 1 +#define ACE_INTL_ML 2 +#define ACE_INTL_IDCA 3 +#define ACE_INTL_LPVML 4 +#define ACE_INTL_SHA 5 +#define ACE_INTL_L1L2M 6 +#define ACE_INTL_I2S 7 +#define ACE_INTL_DMIC 8 +#define ACE_INTL_SNDW 9 +#define ACE_INTL_TTS 10 +#define ACE_INTL_WDT 11 #define ACE_INTL_HDAHIDMA 12 #define ACE_INTL_HDAHODMA 13 #define ACE_INTL_HDALIDMA 14 #define ACE_INTL_HDALODMA 15 -#define ACE_INTL_I3C 16 -#define ACE_INTL_GPDMA 17 -#define ACE_INTL_PWM 18 -#define ACE_INTL_I2C 19 -#define ACE_INTL_SPI 20 -#define ACE_INTL_UART 21 -#define ACE_INTL_GPIO 22 -#define ACE_INTL_UAOL 23 -#define ACE_INTL_IDCB 24 -#define ACE_INTL_DCW 25 -#define ACE_INTL_DTF 26 -#define ACE_INTL_FLV 27 -#define ACE_INTL_DPDMA 28 +#define ACE_INTL_I3C 16 +#define ACE_INTL_GPDMA 17 +#define ACE_INTL_PWM 18 +#define ACE_INTL_I2C 19 +#define ACE_INTL_SPI 20 +#define ACE_INTL_UART 21 +#define ACE_INTL_GPIO 22 +#define ACE_INTL_UAOL 23 +#define ACE_INTL_IDCB 24 +#define ACE_INTL_DCW 25 +#define ACE_INTL_DTF 26 +#define ACE_INTL_FLV 27 +#define ACE_INTL_DPDMA 28 /* Device interrupt control for the low priority interrupts. It * provides per-core masking and status checking: ACE_DINT is an array @@ -71,14 +71,14 @@ struct ace_dint { */ #define DXHIPCIE_REG 0x91040 -#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG) +#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG) #define XTENSA_IRQ_NUM_MASK 0xff #define XTENSA_IRQ_NUM_SHIFT 0 -#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) +#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) /* Convert between IRQ_CONNECT() numbers and ACE_INTL_* interrupts */ -#define ACE_IRQ_NUM_SHIFT 8 -#define ACE_IRQ_NUM_MASK 0xFFU +#define ACE_IRQ_NUM_SHIFT 8 +#define ACE_IRQ_NUM_MASK 0xFFU #define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1) #define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc)) diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h index c91e511c96c0cea..74df3245098d789 100644 --- a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h +++ b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h @@ -44,8 +44,8 @@ struct intel_adsp_ipc { * This clears BUSY on the other side of the connection in IDR register. */ #define INTEL_ADSP_IPC_ACE1X_TDA_DONE 0 -#define INTEL_ADSP_IPC_BUSY BIT(31) -#define INTEL_ADSP_IPC_DONE BIT(31) +#define INTEL_ADSP_IPC_BUSY BIT(31) +#define INTEL_ADSP_IPC_DONE BIT(31) #define INTEL_ADSP_IPC_CTL_TBIE BIT(0) #define INTEL_ADSP_IPC_CTL_IDIE BIT(1) diff --git a/soc/intel/intel_adsp/ace/include/dmic_regs.h b/soc/intel/intel_adsp/ace/include/dmic_regs.h index df69d3687f19d7f..492e320bf4095cf 100644 --- a/soc/intel/intel_adsp/ace/include/dmic_regs.h +++ b/soc/intel/intel_adsp/ace/include/dmic_regs.h @@ -351,7 +351,7 @@ #include #elif CONFIG_SOC_INTEL_ACE15_MTPM #include -#elif CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_ACE30 #include #else #error "Unknown SoC" diff --git a/soc/intel/intel_adsp/ace/mmu_ptl.c b/soc/intel/intel_adsp/ace/mmu_ace30.c similarity index 100% rename from soc/intel/intel_adsp/ace/mmu_ptl.c rename to soc/intel/intel_adsp/ace/mmu_ace30.c diff --git a/soc/intel/intel_adsp/common/clk.c b/soc/intel/intel_adsp/common/clk.c index 3cb4b0e2db72e47..86b82e175168a4b 100644 --- a/soc/intel/intel_adsp/common/clk.c +++ b/soc/intel/intel_adsp/common/clk.c @@ -96,7 +96,7 @@ void adsp_clock_init(void) } else { platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL; } -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_ACE30 /* Set the Cardinal clock divider to 18 to get 24.576MHz */ ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK; ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12); diff --git a/soc/intel/intel_adsp/soc.yml b/soc/intel/intel_adsp/soc.yml index 0f889aea9638218..e797abd9de6fdc2 100644 --- a/soc/intel/intel_adsp/soc.yml +++ b/soc/intel/intel_adsp/soc.yml @@ -5,7 +5,7 @@ family: socs: - name: ace15_mtpm - name: ace20_lnl - - name: ace30_ptl + - name: ace30 - name: intel_adsp_cavs socs: - name: cavs25 diff --git a/tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30_ptl.conf b/tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30_ptl.conf rename to tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30.conf diff --git a/tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30_ptl.conf b/tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30_ptl.conf rename to tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30.conf diff --git a/tests/kernel/queue/boards/intel_adsp_ace30_ptl.conf b/tests/kernel/queue/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/kernel/queue/boards/intel_adsp_ace30_ptl.conf rename to tests/kernel/queue/boards/intel_adsp_ace30.conf diff --git a/tests/lib/c_lib/thrd/boards/intel_adsp_ace30_ptl.conf b/tests/lib/c_lib/thrd/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/lib/c_lib/thrd/boards/intel_adsp_ace30_ptl.conf rename to tests/lib/c_lib/thrd/boards/intel_adsp_ace30.conf