From 2c34da96f0e3ba07764db3ac7def9b400bbd1729 Mon Sep 17 00:00:00 2001 From: Ian Morris Date: Fri, 14 Jun 2024 15:45:14 -0700 Subject: [PATCH] drivers: clock_control: ra: fix issue with setting memwait cycles Setting the number of memory wait cycles must take place while the clock is set to 32MHz or less. This patch ensure the MEMWAIT register is changed before the clock is changed from its default value (of 8MHz). Note that in order to set MEMWAIT to 1 the power control mode must be set to high speed (which is why the lines of code interacting with the OPCCR register have also been moved). Signed-off-by: Ian Morris --- drivers/clock_control/clock_control_renesas_ra.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clock_control/clock_control_renesas_ra.c b/drivers/clock_control/clock_control_renesas_ra.c index 26bb3ab3eb74de..0b058633151cfd 100644 --- a/drivers/clock_control/clock_control_renesas_ra.c +++ b/drivers/clock_control/clock_control_renesas_ra.c @@ -286,6 +286,13 @@ static int clock_control_ra_init(const struct device *dev) } } + SYSTEM_write8(OPCCR_OFFSET, 0); + while ((SYSTEM_read8(OPCCR_OFFSET) & BIT(OPCCR_OPCMTSF_POS)) != 0) { + ; + } + + SYSTEM_write8(MEMWAIT_OFFSET, 1); + SYSTEM_write32(SCKDIVCR_OFFSET, SCKDIVCR_INIT_VALUE); SYSTEM_write8(SCKSCR_OFFSET, SCKSCR_INIT_VALUE); @@ -293,12 +300,6 @@ static int clock_control_ra_init(const struct device *dev) sysclk = SYSTEM_read8(SCKSCR_OFFSET); z_clock_hw_cycles_per_sec = clock_freqs[sysclk]; - SYSTEM_write8(OPCCR_OFFSET, 0); - while ((SYSTEM_read8(OPCCR_OFFSET) & BIT(OPCCR_OPCMTSF_POS)) != 0) { - ; - } - - SYSTEM_write8(MEMWAIT_OFFSET, 1); SYSTEM_write16(PRCR_OFFSET, PRCR_KEY); return 0;