From 2b3c7a9aadb1c49ad32227f30d0287c6c47382b9 Mon Sep 17 00:00:00 2001 From: Jean Nanchen Date: Mon, 17 Jun 2024 08:48:20 +0000 Subject: [PATCH] drivers: sensor: maxim: max31865: Fix fault bit clearing Ensures D1 sets and D5, D3, D2 reset, preventing undefined states. Signed-off-by: Jean Nanchen --- drivers/sensor/maxim/max31865/max31865.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/sensor/maxim/max31865/max31865.c b/drivers/sensor/maxim/max31865/max31865.c index 9fd2fc0108ccecc..02d13986e9706ba 100644 --- a/drivers/sensor/maxim/max31865/max31865.c +++ b/drivers/sensor/maxim/max31865/max31865.c @@ -177,15 +177,21 @@ static char *max31865_error_to_string(uint8_t fault_register) static int max31865_fault_register(const struct device *dev) { uint8_t fault_register; + uint8_t old_d5_d3_d2; max31865_spi_read(dev, (REG_FAULT_STATUS), &fault_register, 1); struct max31865_data *data = dev->data; + old_d5_d3_d2 = data->config_control_bits & 0b00101100; /*Clear fault register */ WRITE_BIT(data->config_control_bits, 1, 1); + WRITE_BIT(data->config_control_bits, 5, 0); + WRITE_BIT(data->config_control_bits, 3, 0); + WRITE_BIT(data->config_control_bits, 2, 0); configure_device(dev); LOG_ERR("Fault Register: 0x%02x, %s", fault_register, max31865_error_to_string(fault_register)); WRITE_BIT(data->config_control_bits, 1, 0); + data->config_control_bits |= old_d5_d3_d2; return 0; }