From 288c39824778f9e3ad21f5ca891fac4c2244f6c2 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 28 Jun 2023 11:28:16 +0300 Subject: [PATCH] nxp: mimx9: Switch to using CCM Rev3 clock controller This commit introduces the necessary changes to the i.MX93 files required to make use of the CCM Rev3 driver. Signed-off-by: Laurentiu Mihalcea --- dts/arm64/nxp/nxp_mimx93_a55.dtsi | 18 +++++++----------- include/zephyr/dt-bindings/clock/imx93_ccm.h | 16 ++++++++++++++++ soc/arm64/nxp_imx/mimx9/mmu_regions.c | 10 ---------- 3 files changed, 23 insertions(+), 21 deletions(-) create mode 100644 include/zephyr/dt-bindings/clock/imx93_ccm.h diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi index 1e73bff224fb09f..0e0650c0e319095 100644 --- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include / { @@ -70,15 +70,11 @@ }; }; - ana_pll: ana_pll@44480000 { - compatible = "nxp,imx-ana"; - reg = <0x44480000 DT_SIZE_K(64)>; - }; - ccm: ccm@44450000 { - compatible = "nxp,imx-ccm"; - reg = <0x44450000 DT_SIZE_K(64)>; - #clock-cells = <3>; + compatible = "nxp,imx-ccm-rev3"; + reg = <0x44450000 DT_SIZE_K(64)>, // CCM base + <0x44480000 DT_SIZE_K(64)>; // PLL base + #clock-cells = <2>; }; lpuart1: serial@44380000 { @@ -87,7 +83,7 @@ interrupts = ; interrupt-names = "irq_0"; interrupt-parent = <&gic>; - clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>; + clocks = <&ccm IMX93_CCM_LPUART1_CLOCK 24000000>; status = "disabled"; }; @@ -97,7 +93,7 @@ interrupts = ; interrupt-names = "irq_0"; interrupt-parent = <&gic>; - clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>; + clocks = <&ccm IMX93_CCM_LPUART2_CLOCK 24000000>; status = "disabled"; }; }; diff --git a/include/zephyr/dt-bindings/clock/imx93_ccm.h b/include/zephyr/dt-bindings/clock/imx93_ccm.h new file mode 100644 index 000000000000000..536441ae01eff3a --- /dev/null +++ b/include/zephyr/dt-bindings/clock/imx93_ccm.h @@ -0,0 +1,16 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX93_CCM_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX93_CCM_H_ + +/* note: the values of these defines need to match the indexes + * in the array of clocks for the clocks they represent. + */ +#define IMX93_CCM_LPUART1_CLOCK 0 +#define IMX93_CCM_LPUART2_CLOCK 1 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX93_CCM_H_ */ diff --git a/soc/arm64/nxp_imx/mimx9/mmu_regions.c b/soc/arm64/nxp_imx/mimx9/mmu_regions.c index fb53c54e7f38f77..ca644c473eb4b9f 100644 --- a/soc/arm64/nxp_imx/mimx9/mmu_regions.c +++ b/soc/arm64/nxp_imx/mimx9/mmu_regions.c @@ -20,16 +20,6 @@ static const struct arm_mmu_region mmu_regions[] = { DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), - MMU_REGION_FLAT_ENTRY("CCM", - DT_REG_ADDR(DT_NODELABEL(ccm)), - DT_REG_SIZE(DT_NODELABEL(ccm)), - MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), - - MMU_REGION_FLAT_ENTRY("ANA_PLL", - DT_REG_ADDR(DT_NODELABEL(ana_pll)), - DT_REG_SIZE(DT_NODELABEL(ana_pll)), - MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), - MMU_REGION_FLAT_ENTRY("UART2", DT_REG_ADDR(DT_NODELABEL(lpuart2)), DT_REG_SIZE(DT_NODELABEL(lpuart2)),