diff --git a/drivers/ethernet/CMakeLists.txt b/drivers/ethernet/CMakeLists.txt
index 53415e391719742..85f534111d9ed16 100644
--- a/drivers/ethernet/CMakeLists.txt
+++ b/drivers/ethernet/CMakeLists.txt
@@ -40,6 +40,7 @@ zephyr_library_sources_ifdef(CONFIG_ETH_IVSHMEM 	eth_ivshmem.c eth_ivshmem_queue
 zephyr_library_sources_ifdef(CONFIG_ETH_ADIN2111	eth_adin2111.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_LAN865X	        eth_lan865x.c oa_tc6.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_XMC4XXX     eth_xmc4xxx.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_LAN9250    eth_lan9250.c)
 
 if(CONFIG_ETH_NXP_S32_NETC)
   zephyr_library_sources(eth_nxp_s32_netc.c)
diff --git a/drivers/ethernet/Kconfig b/drivers/ethernet/Kconfig
index c81fe78e1e2b096..8a81deeba0babdd 100644
--- a/drivers/ethernet/Kconfig
+++ b/drivers/ethernet/Kconfig
@@ -73,6 +73,7 @@ source "drivers/ethernet/Kconfig.adin2111"
 source "drivers/ethernet/Kconfig.numaker"
 source "drivers/ethernet/Kconfig.lan865x"
 source "drivers/ethernet/Kconfig.xmc4xxx"
+source "drivers/ethernet/Kconfig.lan9250"
 
 source "drivers/ethernet/eth_nxp_enet_qos/Kconfig"
 
diff --git a/drivers/ethernet/Kconfig.lan9250 b/drivers/ethernet/Kconfig.lan9250
new file mode 100644
index 000000000000000..041cb7e49dd69ff
--- /dev/null
+++ b/drivers/ethernet/Kconfig.lan9250
@@ -0,0 +1,40 @@
+# LAN9250 Stand-alone Ethernet Controller configuration options
+
+# Copyright (c) 2024 Mario Paja
+# SPDX-License-Identifier: Apache-2.0
+
+
+menuconfig ETH_LAN9250
+	bool "LAN9250 Ethernet Controller"
+	default y
+	depends on DT_HAS_MICROCHIP_LAN9250_ENABLED
+	select SPI
+	help
+	  LAN9250 Stand-Alone Ethernet Controller
+	  with SPI Interface
+
+if ETH_LAN9250
+
+config ETH_LAN9250_RX_THREAD_STACK_SIZE
+	int "Stack size for internal incoming packet handler"
+	default 800
+	help
+	  Size of the stack used for internal thread which is ran for
+	  incoming packet processing.
+
+config ETH_LAN9250_RX_THREAD_PRIO
+	int "Priority for internal incoming packet handler"
+	default 2
+	help
+	  Priority level for internal thread which is ran for incoming
+	  packet processing.
+
+config ETH_LAN9250_BUF_ALLOC_TIMEOUT
+	int "Network buffer allocation timeout"
+	default 100
+	help
+	  Given timeout in milliseconds. Maximum amount of time
+	  that the driver will wait from the IP stack to get
+	  a memory buffer before the Ethernet frame is dropped.
+
+endif
diff --git a/drivers/ethernet/eth_lan9250.c b/drivers/ethernet/eth_lan9250.c
new file mode 100644
index 000000000000000..05ade853953d875
--- /dev/null
+++ b/drivers/ethernet/eth_lan9250.c
@@ -0,0 +1,728 @@
+/* LAN9250 Stand-alone Ethernet Controller with SPI
+ *
+ * Copyright (c) 2024 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT microchip_lan9250
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <string.h>
+#include <errno.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/net/net_pkt.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/ethernet.h>
+#include <ethernet/eth_stats.h>
+
+#include "eth_lan9250_priv.h"
+
+LOG_MODULE_REGISTER(eth_lan9250, CONFIG_ETHERNET_LOG_LEVEL);
+
+static int lan9250_write_sys_reg(const struct device *dev, uint16_t address, uint32_t data)
+{
+	const struct lan9250_config *config = dev->config;
+	uint8_t cmd[1] = {LAN9250_SPI_INSTR_WRITE};
+	uint8_t addr[2] = {(address >> 8) & 0xFF, (address & 0xFF)};
+	uint8_t instr[4] = {(data & 0xFF), (data >> 8 & 0xFF), (data >> 16 & 0xFF),
+			    (data >> 24 & 0xFF)};
+	struct spi_buf tx_buf[3];
+
+	tx_buf[0].buf = &cmd;
+	tx_buf[0].len = ARRAY_SIZE(cmd);
+	tx_buf[1].buf = addr;
+	tx_buf[1].len = ARRAY_SIZE(addr);
+	tx_buf[2].buf = instr;
+	tx_buf[2].len = ARRAY_SIZE(instr);
+
+	struct spi_buf_set tx = {.buffers = tx_buf, .count = 3};
+
+	return spi_write_dt(&config->spi, &tx);
+}
+
+static int lan9250_read_sys_reg(const struct device *dev, uint16_t address, uint32_t *value)
+{
+	const struct lan9250_config *config = dev->config;
+	uint8_t cmd[1] = {LAN9250_SPI_INSTR_READ};
+	uint8_t addr[2] = {(address >> 8) & 0xFF, (address & 0xFF)};
+	struct spi_buf tx_buf[3];
+	struct spi_buf rx_buf[3];
+
+	tx_buf[0].buf = &cmd;
+	tx_buf[0].len = ARRAY_SIZE(cmd);
+	tx_buf[1].buf = addr;
+	tx_buf[1].len = ARRAY_SIZE(addr);
+	tx_buf[2].buf = NULL;
+	tx_buf[2].len = sizeof(uint32_t);
+
+	rx_buf[0].buf = NULL;
+	rx_buf[0].len = 1;
+	rx_buf[1].buf = NULL;
+	rx_buf[1].len = 2;
+	rx_buf[2].buf = value;
+	rx_buf[2].len = sizeof(uint32_t);
+
+	struct spi_buf_set tx = {.buffers = tx_buf, .count = 3};
+	const struct spi_buf_set rx = {.buffers = rx_buf, .count = 3};
+
+	return spi_transceive_dt(&config->spi, &tx, &rx);
+}
+
+static int lan9250_wait_ready(const struct device *dev, uint16_t address, uint32_t mask,
+			      uint32_t expected, uint32_t m_second)
+{
+	uint32_t tmp;
+	int wait_time = 0;
+
+	while (true) {
+		lan9250_read_sys_reg(dev, address, &tmp);
+		wait_time++;
+		k_busy_wait(USEC_PER_MSEC * 1U);
+		if ((tmp & mask) == expected) {
+			return 0;
+		} else if (wait_time == m_second) {
+			LOG_ERR("NOT READY");
+			return -EIO;
+		}
+	}
+}
+
+static int lan9250_read_mac_reg(const struct device *dev, uint8_t address, uint32_t *value)
+{
+	uint32_t tmp;
+
+	/* Wait for MAC to be ready and send writing register command and data */
+	lan9250_wait_ready(dev, LAN9250_MAC_CSR_CMD, LAN9250_MAC_CSR_CMD_BUSY, 0,
+			   LAN9250_MAC_TIMEOUT);
+	lan9250_write_sys_reg(dev, LAN9250_MAC_CSR_CMD,
+			      address | LAN9250_MAC_CSR_CMD_BUSY | LAN9250_MAC_CSR_CMD_READ);
+
+	/* Wait for MAC to be ready and send writing register command and data */
+	lan9250_wait_ready(dev, LAN9250_MAC_CSR_CMD, LAN9250_MAC_CSR_CMD_BUSY, 0,
+			   LAN9250_MAC_TIMEOUT);
+
+	lan9250_read_sys_reg(dev, LAN9250_MAC_CSR_DATA, &tmp);
+
+	*value = tmp;
+	return 0;
+}
+
+static int lan9250_write_mac_reg(const struct device *dev, uint8_t address, uint32_t data)
+{
+	/* Wait for MAC to be ready and send writing register command and data */
+	lan9250_wait_ready(dev, LAN9250_MAC_CSR_CMD, LAN9250_MAC_CSR_CMD_BUSY, 0,
+			   LAN9250_MAC_TIMEOUT);
+	lan9250_write_sys_reg(dev, LAN9250_MAC_CSR_DATA, data);
+	lan9250_write_sys_reg(dev, LAN9250_MAC_CSR_CMD, address | LAN9250_MAC_CSR_CMD_BUSY);
+
+	/* Wait until writing MAC is done */
+	lan9250_wait_ready(dev, LAN9250_MAC_CSR_CMD, LAN9250_MAC_CSR_CMD_BUSY, 0,
+			   LAN9250_MAC_TIMEOUT);
+
+	return 0;
+}
+
+static int lan9250_wait_mac_ready(const struct device *dev, uint8_t address, uint32_t mask,
+				  uint32_t expected, uint32_t m_second)
+{
+	uint32_t tmp;
+	int wait_time = 0;
+
+	while (true) {
+		lan9250_read_mac_reg(dev, address, &tmp);
+		wait_time++;
+		k_msleep(1);
+		if ((tmp & mask) == expected) {
+			return 0;
+		} else if (wait_time == m_second) {
+			return -EIO;
+		}
+	}
+}
+
+static int lan9250_read_phy_reg(const struct device *dev, uint8_t address, uint16_t *value)
+{
+	uint32_t tmp;
+
+	/* Wait PHY to be ready and send reading register command */
+	lan9250_wait_mac_ready(dev, LAN9250_HMAC_MII_ACC, LAN9250_HMAC_MII_ACC_MIIBZY, 0,
+			       LAN9250_PHY_TIMEOUT);
+
+	/* Reference: Microchip Ethernet LAN9250
+	 * https://github.com/microchip-pic-avr-solutions/ethernet-lan9250/
+	 *
+	 * Datasheet:
+	 * https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/00001913A.pdf
+	 *
+	 * 12.2.18 PHY REGISTERS
+	 * The PHY registers are indirectly accessed through the Host MAC MII Access Register
+	 * (HMAC_MII_ACC) and Host MAC MII Data Register (HMAC_MII_DATA).
+	 *
+	 * Write 32bit value to the indirect MAC registers
+	 * Where phy_add = 0b00001 & index = address
+	 * Data = ((phy_add & 0x1F) << 11) | ((index & 0x1F) << 6)
+	 */
+	lan9250_write_mac_reg(dev, LAN9250_HMAC_MII_ACC, (1 << 11) | ((address & 0x1F) << 6));
+
+	/* Wait PHY to be ready and send reading register command */
+	lan9250_wait_mac_ready(dev, LAN9250_HMAC_MII_ACC, LAN9250_HMAC_MII_ACC_MIIBZY, 0,
+			       LAN9250_PHY_TIMEOUT);
+
+	/* Read 32bit value from the indirect MAC registers */
+	lan9250_read_mac_reg(dev, LAN9250_HMAC_MII_DATA, &tmp);
+	*value = tmp;
+
+	return 0;
+}
+
+static int lan9250_write_phy_reg(const struct device *dev, uint8_t address, uint16_t data)
+{
+	/* Wait PHY to be ready and send reading register command */
+	lan9250_wait_mac_ready(dev, LAN9250_HMAC_MII_ACC, LAN9250_HMAC_MII_ACC_MIIBZY, 0,
+			       LAN9250_PHY_TIMEOUT);
+	lan9250_write_mac_reg(dev, LAN9250_HMAC_MII_DATA, data);
+
+	/* Reference: Microchip Ethernet LAN9250
+	 * https://github.com/microchip-pic-avr-solutions/ethernet-lan9250/
+	 *
+	 * Datasheet:
+	 * https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/00001913A.pdf
+	 *
+	 * 12.2.18 PHY REGISTERS
+	 * The PHY registers are indirectly accessed through the Host MAC MII Access Register
+	 * (HMAC_MII_ACC) and Host MAC MII Data Register (HMAC_MII_DATA).
+	 *
+	 * Write 32bit value to the indirect MAC registers
+	 * Where phy_add = 0b00001 & index = address
+	 * Data = ((phy_add & 0x1F) << 11) | ((index & 0x1F)<< 6) | MIIWnR
+	 */
+	lan9250_write_mac_reg(dev, LAN9250_HMAC_MII_ACC,
+			      (1 << 11) | ((address & 0x1F) << 6) | LAN9250_HMAC_MII_ACC_MIIW_R);
+
+	/* Wait PHY to be ready and send reading register command */
+	lan9250_wait_mac_ready(dev, LAN9250_HMAC_MII_ACC, LAN9250_HMAC_MII_ACC_MIIBZY, 0,
+			       LAN9250_PHY_TIMEOUT);
+
+	return 0;
+}
+
+static int lan9250_set_macaddr(const struct device *dev)
+{
+	struct lan9250_runtime *ctx = dev->data;
+
+	lan9250_write_mac_reg(dev, LAN9250_HMAC_ADDRL,
+			      ctx->mac_address[0] | (ctx->mac_address[1] << 8) |
+				      (ctx->mac_address[2] << 16) | (ctx->mac_address[3] << 24));
+	lan9250_write_mac_reg(dev, LAN9250_HMAC_ADDRH,
+			      ctx->mac_address[4] | (ctx->mac_address[5] << 8));
+
+	return 0;
+}
+
+static int lan9250_spi_check(const struct device *dev)
+{
+	uint32_t tmp;
+	uint8_t retries = LAN9250_DEFAULT_NUMOF_RETRIES;
+
+	do {
+		lan9250_read_sys_reg(dev, LAN9250_BYTE_TEST, &tmp);
+		k_busy_wait(USEC_PER_MSEC * 1U);
+	} while (tmp != LAN9250_BYTE_TEST_DEFAULT && retries--);
+
+	return 0;
+}
+
+static int lan9250_hw_cfg_check(const struct device *dev)
+{
+	uint32_t tmp;
+
+	do {
+		lan9250_read_sys_reg(dev, LAN9250_HW_CFG, &tmp);
+		k_busy_wait(USEC_PER_MSEC * 1U);
+	} while ((tmp & LAN9250_HW_CFG_DEVICE_READY) == 0);
+
+	LOG_DBG("LAN9250_HW_CFG OK");
+
+	return 0;
+}
+
+static int lan9250_sw_reset(const struct device *dev)
+{
+	/* Wait until LAN9250 SPI bus is ready */
+	lan9250_wait_ready(dev, LAN9250_BYTE_TEST, BOTR_MASK, LAN9250_BYTE_TEST_DEFAULT,
+			   LAN9250_RESET_TIMEOUT);
+	lan9250_write_sys_reg(dev, LAN9250_RESET_CTL,
+			      LAN9250_RESET_CTL_HMAC_RST | LAN9250_RESET_CTL_PHY_RST |
+				      LAN9250_RESET_CTL_DIGITAL_RST);
+
+	/* Wait until LAN9250 SPI bus is ready */
+	lan9250_wait_ready(dev, LAN9250_BYTE_TEST, BOTR_MASK, LAN9250_BYTE_TEST_DEFAULT,
+			   LAN9250_RESET_TIMEOUT);
+
+	return 0;
+}
+
+static int lan9250_configure(const struct device *dev)
+{
+	uint32_t tmp;
+
+	lan9250_hw_cfg_check(dev);
+
+	/* Read LAN9250 hardware ID */
+	lan9250_read_sys_reg(dev, LAN9250_ID_REV, &tmp);
+	if ((tmp & LAN9250_ID_REV_CHIP_ID) != LAN9250_ID_REV_CHIP_ID_DEFAULT) {
+		LOG_ERR("ERROR: Bad Rev ID: %08x\n", tmp);
+		return -ENODEV;
+	}
+
+	/* Configure TX FIFO size mode to be 8:
+	 *
+	 *   - TX data FIFO size:   7680
+	 *   - RX data FIFO size:   7680
+	 *   - TX status FIFO size: 512
+	 *   - RX status FIFO size: 512
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_HW_CFG,
+			      LAN9250_HW_CFG_MBO | LAN9250_HW_CFG_TX_FIF_SZ_8KB);
+
+	/* Configure MAC automatic flow control:
+	 *
+	 *  Reference: Microchip Ethernet LAN9250
+	 *  https://github.com/microchip-pic-avr-solutions/ethernet-lan9250/
+	 *  LAN_Regwrite32(AFC_CFG, 0x006E3741);
+	 *
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_AFC_CFG, 0x006e3741);
+
+	/* Configure interrupt:
+	 *
+	 *   - Interrupt De-assertion interval: 100
+	 *   - Interrupt output to pin
+	 *   - Interrupt pin active output low
+	 *   - Interrupt pin push-pull driver
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_IRQ_CFG,
+			      LAN9250_IRQ_CFG_INT_DEAS_100US | LAN9250_IRQ_CFG_IRQ_EN |
+				      LAN9250_IRQ_CFG_IRQ_TYPE_PP);
+
+	/* Configure interrupt trigger source, please refer to macro
+	 * LAN9250_INT_SOURCE.
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_INT_EN,
+			      LAN9250_INT_EN_PHY_INT_EN | LAN9250_INT_EN_TDFA_EN |
+				      LAN9250_INT_EN_RSFL_EN);
+
+	/* Disable TX data FIFO available interrupt */
+	lan9250_write_sys_reg(dev, LAN9250_FIFO_INT,
+			      LAN9250_FIFO_INT_TX_DATA_AVAILABLE_LEVEL |
+				      LAN9250_FIFO_INT_TX_STATUS_LEVEL);
+
+	/* Configure RX:
+	 *
+	 *   - RX DMA counter: Ethernet maximum packet size
+	 *   - RX data offset: 4, so that need read dummy before reading data
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_RX_CFG, (NET_ETH_MAX_FRAME_SIZE << 16) | (4 << 8));
+
+	/* Configure remote power management:
+	 *
+	 *   - Auto wakeup
+	 *   - Disable 1588 clock
+	 *   - Disable 1588 timestamp unit clock
+	 *   - Energy-detect
+	 *   - Wake on
+	 *   - PME pin push-pull driver
+	 *   - Clear wakeon
+	 *   - PME active high
+	 *   - PME pin
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_PMT_CTRL,
+			      LAN9250_PMT_CTRL_PM_WAKE | LAN9250_PMT_CTRL_1588_DIS |
+				      LAN9250_PMT_CTRL_1588_TSU_DIS | LAN9250_PMT_CTRL_ED_EN |
+				      LAN9250_PMT_CTRL_WOL_EN | LAN9250_PMT_CTRL_PME_TYPE |
+				      LAN9250_PMT_CTRL_WOL_STS | LAN9250_PMT_CTRL_PME_POL |
+				      LAN9250_PMT_CTRL_PME_EN);
+
+	/* Configure PHY basic control:
+	 *
+	 *   - Auto-Negotiation for 10/100 Mbits and Half/Full Duplex
+	 */
+	lan9250_write_phy_reg(dev, LAN9250_PHY_BASIC_CONTROL,
+			      LAN9250_PHY_BASIC_CONTROL_PHY_AN |
+				      LAN9250_PHY_BASIC_CONTROL_PHY_SPEED_SEL_LSB |
+				      LAN9250_PHY_BASIC_CONTROL_PHY_DUPLEX);
+
+	/* Configure PHY auto-negotiation advertisement capability:
+	 *
+	 *   - Asymmetric pause
+	 *   - Symmetric pause
+	 *   - 100Base-X half/full duplex
+	 *   - 10Base-X half/full duplex
+	 *   - Select IEEE802.3
+	 */
+	lan9250_write_phy_reg(dev, LAN9250_PHY_AN_ADV,
+			      LAN9250_PHY_AN_ADV_ASYM_PAUSE | LAN9250_PHY_AN_ADV_SYM_PAUSE |
+				      LAN9250_PHY_AN_ADV_100BTX_HD | LAN9250_PHY_AN_ADV_100BTX_FD |
+				      LAN9250_PHY_AN_ADV_10BT_HD | LAN9250_PHY_AN_ADV_10BT_FD |
+				      LAN9250_PHY_AN_ADV_SELECTOR_DEFAULT);
+
+	/* Configure PHY special mode:
+	 *
+	 *   - PHY mode = 111b, enable all capable and auto-nagotiation
+	 *   - PHY address = 1, default value is fixed to 1 by manufacturer
+	 */
+	lan9250_write_phy_reg(dev, LAN9250_PHY_SPECIAL_MODES, 0x00E0 | 1);
+
+	/* Configure PHY special control or status indication:
+	 *
+	 *   - Port auto-MDIX determined by bits 14 and 13
+	 *   - Auto-MDIX
+	 *   - Disable SQE tests
+	 */
+	lan9250_write_phy_reg(dev, LAN9250_PHY_SPECIAL_CONTROL_STAT_IND,
+			      LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXCTRL |
+				      LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXEN |
+				      LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_SQEOFF);
+
+	/* Configure PHY interrupt source:
+	 *
+	 *   - Link up
+	 *   - Link down
+	 */
+	lan9250_write_phy_reg(dev, LAN9250_PHY_INTERRUPT_MASK,
+			      LAN9250_PHY_INTERRUPT_SOURCE_LINK_UP |
+				      LAN9250_PHY_INTERRUPT_SOURCE_LINK_DOWN);
+
+	/* Configure special control or status:
+	 *
+	 *   - Fixed to write 0000010b to reserved filed
+	 */
+	lan9250_write_phy_reg(dev, LAN9250_PHY_SPECIAL_CONTROL_STATUS,
+			      LAN9250_PHY_MODE_CONTROL_STATUS_ALTINT);
+
+	/* Clear interrupt status */
+	lan9250_write_sys_reg(dev, LAN9250_INT_STS, 0xFFFFFFFF);
+
+	/* Configure HMAC control:
+	 *
+	 *   - Automatically strip the pad field on incoming packets
+	 *   - TX enable
+	 *   - RX enable
+	 *   - Full duplex
+	 */
+	lan9250_write_mac_reg(dev, LAN9250_HMAC_CR,
+			      LAN9250_HMAC_CR_PADSTR | LAN9250_HMAC_CR_TXEN | LAN9250_HMAC_CR_RXEN |
+				      LAN9250_HMAC_CR_FDPX | LAN9250_HMAC_CR_HPFILT |
+				      LAN9250_HMAC_CR_BCAST);
+
+	/** Configure TX:
+	 *
+	 *   - TX enable
+	 */
+	lan9250_write_sys_reg(dev, LAN9250_TX_CFG, LAN9250_TX_CFG_TX_ON);
+
+	return 0;
+}
+
+static int lan9250_write_buf(const struct device *dev, uint8_t *data_buffer, uint16_t buf_len)
+{
+	const struct lan9250_config *config = dev->config;
+	uint8_t cmd[1] = {LAN9250_SPI_INSTR_WRITE};
+	uint8_t instr[2] = {(LAN9250_TX_DATA_FIFO >> 8) & 0xFF, (LAN9250_TX_DATA_FIFO & 0xFF)};
+	struct spi_buf tx_buf[3];
+
+	tx_buf[0].buf = &cmd;
+	tx_buf[0].len = ARRAY_SIZE(cmd);
+	tx_buf[1].buf = &instr;
+	tx_buf[1].len = ARRAY_SIZE(instr);
+	tx_buf[2].buf = data_buffer;
+	tx_buf[2].len = buf_len;
+
+	struct spi_buf_set tx = {.buffers = tx_buf, .count = 3};
+
+	return spi_transceive_dt(&config->spi, &tx, NULL);
+}
+
+static int lan9250_read_buf(const struct device *dev, uint8_t *data_buffer, uint16_t buf_len)
+{
+	const struct lan9250_config *config = dev->config;
+	uint8_t cmd[1] = {LAN9250_SPI_INSTR_READ};
+	uint8_t instr[2] = {(LAN9250_RX_DATA_FIFO >> 8) & 0xFF, (LAN9250_RX_DATA_FIFO & 0xFF)};
+	struct spi_buf tx_buf[3];
+	struct spi_buf rx_buf[3];
+
+	tx_buf[0].buf = &cmd;
+	tx_buf[0].len = ARRAY_SIZE(cmd);
+	tx_buf[1].buf = &instr;
+	tx_buf[1].len = ARRAY_SIZE(instr);
+	tx_buf[2].buf = NULL;
+	tx_buf[2].len = buf_len;
+
+	rx_buf[0].buf = NULL;
+	rx_buf[0].len = 1;
+	rx_buf[1].buf = NULL;
+	rx_buf[1].len = 2;
+	rx_buf[2].buf = data_buffer;
+	rx_buf[2].len = buf_len;
+
+	struct spi_buf_set tx = {.buffers = tx_buf, .count = 3};
+	const struct spi_buf_set rx = {.buffers = rx_buf, .count = 3};
+
+	return spi_transceive_dt(&config->spi, &tx, &rx);
+}
+
+static int lan9250_rx(const struct device *dev)
+{
+	const struct lan9250_config *config = dev->config;
+	struct lan9250_runtime *ctx = dev->data;
+	uint8_t pktcnt;
+	uint32_t tmp;
+	uint16_t pkt_len;
+	uint16_t lengthfr;
+	uint8_t dummy[4];
+
+	/* Check valid packet count in RX FIFO */
+	lan9250_read_sys_reg(dev, LAN9250_RX_FIFO_INF, &tmp);
+	pktcnt = (tmp & LAN9250_RX_FIFO_INF_RXSUSED) >> 16;
+	if (!pktcnt) {
+		return 0;
+	}
+
+	k_sem_take(&ctx->tx_rx_sem, K_FOREVER);
+	lan9250_write_sys_reg(dev, LAN9250_INT_EN, 0);
+
+	while (pktcnt--) {
+		struct net_buf *pkt_buf;
+		struct net_pkt *pkt;
+
+		/* Get the length of the packet */
+		lan9250_read_sys_reg(dev, LAN9250_RX_STATUS_FIFO, &tmp);
+
+		pkt_len = (tmp & LAN9250_RX_STS_PACKET_LEN) >> 16;
+		pkt_len -= 4;
+		lengthfr = pkt_len;
+
+		/* Get the frame from the buffer */
+		pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, pkt_len, AF_UNSPEC, 0,
+						   K_MSEC(config->timeout));
+		if (!pkt) {
+			LOG_ERR("%s: Could not allocate rx buffer", dev->name);
+			eth_stats_update_errors_rx(ctx->iface);
+			return 0;
+		}
+
+		pkt_buf = pkt->buffer;
+
+		lan9250_read_sys_reg(dev, LAN9250_RX_DATA_FIFO, &tmp);
+
+		do {
+			size_t frag_len;
+			uint8_t *data_ptr;
+			size_t spi_frame_len;
+
+			data_ptr = pkt_buf->data;
+
+			/* Review the space available for the new frag */
+			frag_len = net_buf_tailroom(pkt_buf);
+			if (pkt_len > frag_len) {
+				spi_frame_len = frag_len;
+			} else {
+				spi_frame_len = pkt_len;
+			}
+
+			/* Review the space available for the new frag */
+			lan9250_read_buf(dev, data_ptr, spi_frame_len);
+			net_buf_add(pkt_buf, pkt_len);
+
+			pkt_len -= spi_frame_len;
+			pkt_buf = pkt_buf->frags;
+
+		} while (pkt_len > 0);
+
+		lan9250_read_buf(dev, dummy, 4);
+		net_pkt_set_iface(pkt, ctx->iface);
+
+		/* Feed buffer frame to IP stack */
+		if (net_recv_data(net_pkt_iface(pkt), pkt) < 0) {
+			net_pkt_unref(pkt);
+		}
+	}
+	lan9250_write_sys_reg(dev, LAN9250_INT_EN,
+			      LAN9250_INT_EN_PHY_INT_EN | LAN9250_INT_EN_TDFA_EN |
+				      LAN9250_INT_EN_RSFL_EN);
+	k_sem_give(&ctx->tx_rx_sem);
+
+	return 0;
+}
+
+static int lan9250_tx(const struct device *dev, struct net_pkt *pkt)
+{
+	struct lan9250_runtime *ctx = dev->data;
+	size_t len = net_pkt_get_len(pkt);
+	uint32_t regval;
+	uint16_t free_size;
+	uint8_t status_size;
+	uint32_t tmp;
+
+	LOG_DBG("%s: pkt %p (len %u)", dev->name, pkt, len);
+
+	lan9250_read_sys_reg(dev, LAN9250_TX_FIFO_INF, &regval);
+	status_size = (regval & LAN9250_TX_FIFO_INF_TXSUSED) >> 16;
+	free_size = regval & LAN9250_TX_FIFO_INF_TXFREE;
+
+	LOG_DBG("status_size:%d, free_size:%d", status_size, free_size);
+
+	/* Clear TX status FIFO if it is no empty by reading data */
+	k_sem_take(&ctx->tx_rx_sem, K_FOREVER);
+
+	/* TX command 'A' */
+	lan9250_write_sys_reg(dev, LAN9250_TX_DATA_FIFO,
+			      LAN9250_TX_CMD_A_INT_ON_COMP | LAN9250_TX_CMD_A_BUFFER_ALIGN_4B |
+				      LAN9250_TX_CMD_A_START_OFFSET_0B |
+				      LAN9250_TX_CMD_A_FIRST_SEG | LAN9250_TX_CMD_A_LAST_SEG | len);
+
+	/* TX command 'B' */
+	lan9250_write_sys_reg(dev, LAN9250_TX_DATA_FIFO, LAN9250_TX_CMD_B_PACKET_TAG | len);
+
+	if (net_pkt_read(pkt, ctx->buf, len)) {
+		return -EIO;
+	}
+
+	lan9250_write_buf(dev, ctx->buf, LAN9250_ALIGN(len));
+
+	for (int i = 0; i < status_size; i++) {
+		lan9250_read_sys_reg(dev, LAN9250_TX_STATUS_FIFO, &tmp);
+	}
+
+	k_sem_give(&ctx->tx_rx_sem);
+
+	return 0;
+}
+
+static void lan9250_gpio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	struct lan9250_runtime *context = CONTAINER_OF(cb, struct lan9250_runtime, gpio_cb);
+
+	k_sem_give(&context->int_sem);
+}
+
+static void lan9250_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct lan9250_runtime *context = p1;
+	uint32_t isr;
+	uint16_t tmp;
+
+	while (true) {
+		k_sem_take(&context->int_sem, K_FOREVER);
+		lan9250_read_sys_reg(context->dev, LAN9250_INT_STS, &isr);
+
+		if ((isr & LAN9250_INT_STS_PHY_INT) != 0) {
+			/* Read PHY interrupt source register */
+			lan9250_read_phy_reg(context->dev, LAN9250_PHY_INTERRUPT_SOURCE, &tmp);
+
+			if (tmp & LAN9250_PHY_INTERRUPT_SOURCE_LINK_UP) {
+				LOG_DBG("LINK UP");
+				net_eth_carrier_on(context->iface);
+			} else if (tmp & LAN9250_PHY_INTERRUPT_SOURCE_LINK_DOWN) {
+				LOG_DBG("LINK DOWN");
+				net_eth_carrier_off(context->iface);
+			}
+		}
+
+		if ((isr & LAN9250_INT_STS_RSFL) != 0) {
+			lan9250_rx(context->dev);
+		}
+		lan9250_write_sys_reg(context->dev, LAN9250_INT_STS, 0xFFFFFFFF);
+	}
+}
+
+static enum ethernet_hw_caps lan9250_get_capabilities(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T;
+}
+
+static void lan9250_iface_init(struct net_if *iface)
+{
+	const struct device *dev = net_if_get_device(iface);
+	struct lan9250_runtime *context = dev->data;
+
+	net_if_set_link_addr(iface, context->mac_address, sizeof(context->mac_address),
+			     NET_LINK_ETHERNET);
+	context->iface = iface;
+	ethernet_init(iface);
+
+	net_if_carrier_off(iface);
+}
+
+static const struct ethernet_api api_funcs = {
+	.iface_api.init = lan9250_iface_init,
+	.get_capabilities = lan9250_get_capabilities,
+	.send = lan9250_tx,
+};
+
+static int lan9250_init(const struct device *dev)
+{
+	const struct lan9250_config *config = dev->config;
+	struct lan9250_runtime *context = dev->data;
+
+	context->dev = dev;
+
+	/* SPI config */
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("SPI master port %s not ready", config->spi.bus->name);
+		return -EINVAL;
+	}
+
+	/* Initialize GPIO */
+	if (!gpio_is_ready_dt(&config->interrupt)) {
+		LOG_ERR("GPIO port %s not ready", config->interrupt.port->name);
+		return -EINVAL;
+	}
+
+	if (gpio_pin_configure_dt(&config->interrupt, GPIO_INPUT)) {
+		LOG_ERR("Unable to configure GPIO pin %u", config->interrupt.pin);
+		return -EINVAL;
+	}
+
+	gpio_init_callback(&(context->gpio_cb), lan9250_gpio_callback, BIT(config->interrupt.pin));
+	if (gpio_add_callback(config->interrupt.port, &(context->gpio_cb))) {
+		return -EINVAL;
+	}
+
+	gpio_pin_interrupt_configure_dt(&config->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+
+	lan9250_spi_check(dev);
+	lan9250_sw_reset(dev);
+	lan9250_configure(dev);
+	lan9250_set_macaddr(dev);
+
+	k_thread_create(&context->thread, context->thread_stack,
+			CONFIG_ETH_LAN9250_RX_THREAD_STACK_SIZE, lan9250_thread, context, NULL,
+			NULL, K_PRIO_COOP(CONFIG_ETH_LAN9250_RX_THREAD_PRIO), 0, K_NO_WAIT);
+
+	LOG_INF("LAN9250 Initialized");
+
+	return 0;
+}
+
+static struct lan9250_runtime lan9250_0_runtime = {
+	.mac_address = DT_INST_PROP(0, local_mac_address),
+	.tx_rx_sem = Z_SEM_INITIALIZER(lan9250_0_runtime.tx_rx_sem, 1, UINT_MAX),
+	.int_sem = Z_SEM_INITIALIZER(lan9250_0_runtime.int_sem, 0, UINT_MAX),
+};
+
+static const struct lan9250_config lan9250_0_config = {
+	.spi = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
+	.interrupt = GPIO_DT_SPEC_INST_GET(0, int_gpios),
+	.timeout = CONFIG_ETH_LAN9250_BUF_ALLOC_TIMEOUT,
+};
+
+ETH_NET_DEVICE_DT_INST_DEFINE(0, lan9250_init, NULL, &lan9250_0_runtime, &lan9250_0_config,
+			      CONFIG_ETH_INIT_PRIORITY, &api_funcs, NET_ETH_MTU);
diff --git a/drivers/ethernet/eth_lan9250_priv.h b/drivers/ethernet/eth_lan9250_priv.h
new file mode 100644
index 000000000000000..074d473450dfa1d
--- /dev/null
+++ b/drivers/ethernet/eth_lan9250_priv.h
@@ -0,0 +1,309 @@
+/* LAN9250 Stand-alone Ethernet Controller with SPI
+ *
+ * Copyright (c) 2024 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+
+#ifndef _LAN9250_
+#define _LAN9250_
+
+#define LAN9250_DEFAULT_NUMOF_RETRIES 3U
+#define LAN9250_PHY_TIMEOUT           2000
+#define LAN9250_MAC_TIMEOUT           2000
+#define LAN9250_RESET_TIMEOUT         5000
+
+#define LAN9250_ALIGN(v) (((v) + 3) & (~3))
+
+/* SPI instructions */
+#define LAN9250_SPI_INSTR_WRITE 0x02
+#define LAN9250_SPI_INSTR_READ  0x03
+
+/* TX command 'A' format */
+#define LAN9250_TX_CMD_A_INT_ON_COMP     0x80000000
+#define LAN9250_TX_CMD_A_BUFFER_ALIGN_4B 0x00000000
+#define LAN9250_TX_CMD_A_START_OFFSET_0B 0x00000000
+#define LAN9250_TX_CMD_A_FIRST_SEG       0x00002000
+#define LAN9250_TX_CMD_A_LAST_SEG        0x00001000
+
+/* TX command 'B' format */
+#define LAN9250_TX_CMD_B_PACKET_TAG 0xFFFF0000
+
+/* RX status format */
+#define LAN9250_RX_STS_PACKET_LEN 0x3FFF0000
+
+/* LAN9250 System registers */
+#define LAN9250_RX_DATA_FIFO   0x0000
+#define LAN9250_TX_DATA_FIFO   0x0020
+#define LAN9250_RX_STATUS_FIFO 0x0040
+#define LAN9250_TX_STATUS_FIFO 0x0048
+#define LAN9250_ID_REV         0x0050
+#define LAN9250_IRQ_CFG        0x0054
+#define LAN9250_INT_STS        0x0058
+#define LAN9250_INT_EN         0x005C
+#define LAN9250_BYTE_TEST      0x0064
+#define LAN9250_FIFO_INT       0x0068
+#define LAN9250_RX_CFG         0x006C
+#define LAN9250_TX_CFG         0x0070
+#define LAN9250_HW_CFG         0x0074
+#define LAN9250_RX_FIFO_INF    0x007C
+#define LAN9250_TX_FIFO_INF    0x0080
+#define LAN9250_PMT_CTRL       0x0084
+#define LAN9250_MAC_CSR_CMD    0x00A4
+#define LAN9250_MAC_CSR_DATA   0x00A8
+#define LAN9250_AFC_CFG        0x00AC
+#define LAN9250_RESET_CTL      0x01F8
+
+/* LAN9250 Host MAC registers */
+#define LAN9250_HMAC_CR       0x01
+#define LAN9250_HMAC_ADDRH    0x02
+#define LAN9250_HMAC_ADDRL    0x03
+#define LAN9250_HMAC_MII_ACC  0x06
+#define LAN9250_HMAC_MII_DATA 0x07
+
+/* LAN9250 PHY registers */
+#define LAN9250_PHY_BASIC_CONTROL            0x00
+#define LAN9250_PHY_AN_ADV                   0x04
+#define LAN9250_PHY_SPECIAL_MODES            0x12
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND 0x1B
+#define LAN9250_PHY_INTERRUPT_SOURCE         0x1D
+#define LAN9250_PHY_INTERRUPT_MASK           0x1E
+#define LAN9250_PHY_SPECIAL_CONTROL_STATUS   0x1F
+
+/* Interrupt Configuration register */
+#define LAN9250_IRQ_CFG_INT_DEAS_100US 0xA0000000
+#define LAN9250_IRQ_CFG_IRQ_EN         BIT(8)
+#define LAN9250_IRQ_CFG_IRQ_TYPE_PP    BIT(0)
+
+/* INTERRUPT STATUS REGISTER (INT_STS) */
+#define LAN9250_INT_STS_SW_INT       BIT(31)
+#define LAN9250_INT_STS_DEVICE_READY BIT(30)
+#define LAN9250_INT_STS_1588_EVNT    BIT(29)
+#define LAN9250_INT_STS_PHY_INT      BIT(26)
+#define LAN9250_INT_STS_TXSTOP_INT   BIT(25)
+#define LAN9250_INT_STS_RXSTOP_INT   BIT(24)
+#define LAN9250_INT_STS_RXDFH_INT    BIT(23)
+#define LAN9250_INT_STS_TX_IOC       BIT(21)
+#define LAN9250_INT_STS_RXD_INT      BIT(20)
+#define LAN9250_INT_STS_GPT_INT      BIT(19)
+#define LAN9250_INT_STS_PME_INT      BIT(17)
+#define LAN9250_INT_STS_TXSO         BIT(16)
+#define LAN9250_INT_STS_RWT          BIT(15)
+#define LAN9250_INT_STS_RXE          BIT(14)
+#define LAN9250_INT_STS_TXE          BIT(13)
+#define LAN9250_INT_STS_GPIO         BIT(12)
+#define LAN9250_INT_STS_TDFO         BIT(10)
+#define LAN9250_INT_STS_TDFA         BIT(9)
+#define LAN9250_INT_STS_TSFF         BIT(8)
+#define LAN9250_INT_STS_TSFL         BIT(7)
+#define LAN9250_INT_STS_RXDF_INT     BIT(6)
+#define LAN9250_INT_STS_RSFF         BIT(4)
+#define LAN9250_INT_STS_RSFL         BIT(3)
+
+/* INTERRUPT ENABLE REGISTER (INT_EN) */
+#define LAN9250_INT_EN_SW_INT_EN     BIT(31)
+#define LAN9250_INT_EN_READY_EN      BIT(30)
+#define LAN9250_INT_EN_1588_EVNT_EN  BIT(29)
+#define LAN9250_INT_EN_PHY_INT_EN    BIT(26)
+#define LAN9250_INT_EN_TXSTOP_INT_EN BIT(25)
+#define LAN9250_INT_EN_RXSTOP_INT_EN BIT(24)
+#define LAN9250_INT_EN_RXDFH_INT_EN  BIT(23)
+#define LAN9250_INT_EN_TIOC_INT_EN   BIT(21)
+#define LAN9250_INT_EN_RXD_INT_EN    BIT(20)
+#define LAN9250_INT_EN_GPT_INT_EN    BIT(19)
+#define LAN9250_INT_EN_PME_INT_EN    BIT(17)
+#define LAN9250_INT_EN_TXSO_EN       BIT(16)
+#define LAN9250_INT_EN_RWT_INT_EN    BIT(15)
+#define LAN9250_INT_EN_RXE_INT_EN    BIT(14)
+#define LAN9250_INT_EN_TXE_INT_EN    BIT(13)
+#define LAN9250_INT_EN_GPIO_EN       BIT(12)
+#define LAN9250_INT_EN_TDFO_EN       BIT(10)
+#define LAN9250_INT_EN_TDFA_EN       BIT(9)
+#define LAN9250_INT_EN_TSFF_EN       BIT(8)
+#define LAN9250_INT_EN_TSFL_EN       BIT(7)
+#define LAN9250_INT_EN_RXDF_INT_EN   BIT(6)
+#define LAN9250_INT_EN_RSFF_EN       BIT(4)
+#define LAN9250_INT_EN_RSFL_EN       BIT(3)
+
+/* Byte Order Test register */
+#define LAN9250_BYTE_TEST_DEFAULT 0x87654321
+#define BOTR_MASK                 0xffffffff
+
+/* FIFO Level Interrupt register */
+#define LAN9250_FIFO_INT_TX_DATA_AVAILABLE_LEVEL 0xFF000000
+#define LAN9250_FIFO_INT_TX_STATUS_LEVEL         0x00FF0000
+#define LAN9250_FIFO_INT_RX_STATUS_LEVEL         0x000000FF
+
+/* TRANSMIT CONFIGURATION REGISTER (TX_CFG) */
+#define LAN9250_TX_CFG_TXS_DUMP BIT(15)
+#define LAN9250_TX_CFG_TXD_DUMP BIT(14)
+#define LAN9250_TX_CFG_TXSAO    BIT(2)
+#define LAN9250_TX_CFG_TX_ON    BIT(1)
+#define LAN9250_TX_CFG_STOP_TX  BIT(0)
+
+/* HARDWARE CONFIGURATION REGISTER (HW_CFG) */
+#define LAN9250_HW_CFG_DEVICE_READY         BIT(27)
+#define LAN9250_HW_CFG_AMDIX_EN_STRAP_STATE BIT(25)
+#define LAN9250_HW_CFG_MBO                  BIT(20)
+#define LAN9250_HW_CFG_TX_FIF_SZ            0x000F0000
+#define LAN9250_HW_CFG_TX_FIF_SZ_2KB        0x00020000
+#define LAN9250_HW_CFG_TX_FIF_SZ_3KB        0x00030000
+#define LAN9250_HW_CFG_TX_FIF_SZ_4KB        0x00040000
+#define LAN9250_HW_CFG_TX_FIF_SZ_5KB        0x00050000
+#define LAN9250_HW_CFG_TX_FIF_SZ_6KB        0x00060000
+#define LAN9250_HW_CFG_TX_FIF_SZ_7KB        0x00070000
+#define LAN9250_HW_CFG_TX_FIF_SZ_8KB        0x00080000
+#define LAN9250_HW_CFG_TX_FIF_SZ_9KB        0x00090000
+#define LAN9250_HW_CFG_TX_FIF_SZ_10KB       0x000A0000
+#define LAN9250_HW_CFG_TX_FIF_SZ_11KB       0x000B0000
+#define LAN9250_HW_CFG_TX_FIF_SZ_12KB       0x000C0000
+#define LAN9250_HW_CFG_TX_FIF_SZ_13KB       0x000D0000
+#define LAN9250_HW_CFG_TX_FIF_SZ_14KB       0x000E0000
+
+/* RX FIFO Information register */
+#define LAN9250_RX_FIFO_INF_RXSUSED 0x00FF0000
+#define LAN9250_RX_FIFO_INF_RXDUSED 0x0000FFFF
+
+/* TX FIFO Information register */
+#define LAN9250_TX_FIFO_INF_TXSUSED 0x00FF0000
+#define LAN9250_TX_FIFO_INF_TXFREE  0x0000FFFF
+
+/* Power Management Control Register (PMT_CTRL) */
+#define LAN9250_PMT_CTRL_PM_SLEEP_EN       BIT(28)
+#define LAN9250_PMT_CTRL_PM_WAKE           BIT(27)
+#define LAN9250_PMT_CTRL_LED_DIS           BIT(26)
+#define LAN9250_PMT_CTRL_1588_DIS          BIT(25)
+#define LAN9250_PMT_CTRL_1588_TSU_DIS      BIT(22)
+#define LAN9250_PMT_CTRL_HMAC_DIS          BIT(19)
+#define LAN9250_PMT_CTRL_HMAC_SYS_ONLY_DIS BIT(18)
+#define LAN9250_PMT_CTRL_ED_STS            BIT(16)
+#define LAN9250_PMT_CTRL_ED_EN             BIT(14)
+#define LAN9250_PMT_CTRL_WOL_EN            BIT(9)
+#define LAN9250_PMT_CTRL_PME_TYPE          BIT(6)
+#define LAN9250_PMT_CTRL_WOL_STS           BIT(5)
+#define LAN9250_PMT_CTRL_PME_IND           BIT(3)
+#define LAN9250_PMT_CTRL_PME_POL           BIT(2)
+#define LAN9250_PMT_CTRL_PME_EN            BIT(1)
+#define LAN9250_PMT_CTRL_READY             BIT(0)
+
+/* HOST MAC CSR INTERFACE COMMAND REGISTER (MAC_CSR_CMD) */
+#define LAN9250_MAC_CSR_CMD_BUSY BIT(31)
+#define LAN9250_MAC_CSR_CMD_READ BIT(30)
+
+/* Reset Control Register (RESET_CTL) */
+#define LAN9250_RESET_CTL_HMAC_RST    BIT(5)
+#define LAN9250_RESET_CTL_PHY_RST     BIT(1)
+#define LAN9250_RESET_CTL_DIGITAL_RST BIT(0)
+
+/* HOST MAC CONTROL REGISTER (HMAC_CR) */
+#define LAN9250_HMAC_CR_RXALL           BIT(31)
+#define LAN9250_HMAC_CR_HMAC_EEE_ENABLE BIT(25)
+#define LAN9250_HMAC_CR_RCVOWN          BIT(23)
+#define LAN9250_HMAC_CR_LOOPBK          BIT(21)
+#define LAN9250_HMAC_CR_FDPX            BIT(20)
+#define LAN9250_HMAC_CR_MCPAS           BIT(19)
+#define LAN9250_HMAC_CR_PRMS            BIT(18)
+#define LAN9250_HMAC_CR_INVFILT         BIT(17)
+#define LAN9250_HMAC_CR_PASSBAD         BIT(16)
+#define LAN9250_HMAC_CR_HO              BIT(15)
+#define LAN9250_HMAC_CR_HPFILT          BIT(13)
+#define LAN9250_HMAC_CR_BCAST           BIT(11)
+#define LAN9250_HMAC_CR_DISRTY          BIT(10)
+#define LAN9250_HMAC_CR_PADSTR          BIT(8)
+#define LAN9250_HMAC_CR_DFCHK           BIT(5)
+#define LAN9250_HMAC_CR_TXEN            BIT(3)
+#define LAN9250_HMAC_CR_RXEN            BIT(2)
+
+/* HOST MAC MII ACCESS REGISTER (HMAC_MII_ACC) */
+#define LAN9250_HMAC_MII_ACC_MIIW_R BIT(1)
+#define LAN9250_HMAC_MII_ACC_MIIBZY BIT(0)
+
+/* PHY Basic Control Register (PHY_BASIC_CONTROL) */
+#define LAN9250_PHY_BASIC_CONTROL_PHY_SRST          BIT(15)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_LOOPBACK      BIT(14)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_SPEED_SEL_LSB BIT(13)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_AN            BIT(12)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_PWR_DWN       BIT(11)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_RST_AN        BIT(9)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_DUPLEX        BIT(8)
+#define LAN9250_PHY_BASIC_CONTROL_PHY_COL_TEST      BIT(7)
+
+/* PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) */
+#define LAN9250_PHY_AN_ADV_NEXT_PAGE          BIT(15)
+#define LAN9250_PHY_AN_ADV_REMOTE_FAULT       BIT(13)
+#define LAN9250_PHY_AN_ADV_EXTENDED_NEXT_PAGE BIT(12)
+#define LAN9250_PHY_AN_ADV_ASYM_PAUSE         BIT(11)
+#define LAN9250_PHY_AN_ADV_SYM_PAUSE          BIT(10)
+#define LAN9250_PHY_AN_ADV_100BTX_FD          BIT(8)
+#define LAN9250_PHY_AN_ADV_100BTX_HD          BIT(7)
+#define LAN9250_PHY_AN_ADV_10BT_FD            BIT(6)
+#define LAN9250_PHY_AN_ADV_10BT_HD            BIT(5)
+#define LAN9250_PHY_AN_ADV_SELECTOR_DEFAULT   BIT(1)
+
+/* PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS) */
+#define LAN9250_PHY_MODE_CONTROL_STATUS_EDPWRDOWN BIT(13)
+#define LAN9250_PHY_MODE_CONTROL_STATUS_ALTINT    BIT(6)
+#define LAN9250_PHY_MODE_CONTROL_STATUS_ENERGYON  BIT(1)
+
+/* PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND) */
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXCTRL  BIT(15)
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXEN    BIT(14)
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXSTATE BIT(13)
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_SQEOFF     BIT(11)
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_FEFI_EN    BIT(5)
+#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_XPOL       BIT(4)
+
+/* PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE) */
+#define LAN9250_PHY_INTERRUPT_SOURCE_LINK_UP               BIT(9)
+#define LAN9250_PHY_INTERRUPT_SOURCE_ENERGYON              BIT(7)
+#define LAN9250_PHY_INTERRUPT_SOURCE_AN_COMPLETE           BIT(6)
+#define LAN9250_PHY_INTERRUPT_SOURCE_REMOTE_FAULT          BIT(5)
+#define LAN9250_PHY_INTERRUPT_SOURCE_LINK_DOWN             BIT(4)
+#define LAN9250_PHY_INTERRUPT_SOURCE_AN_LP_ACK             BIT(3)
+#define LAN9250_PHY_INTERRUPT_SOURCE_PARALLEL_DETECT_FAULT BIT(2)
+#define LAN9250_PHY_INTERRUPT_SOURCE_AN_PAGE_RECEIVED      BIT(1)
+
+/* PHY Interrupt Mask Register (PHY_INTERRUPT_MASK) */
+#define LAN9250_PHY_INTERRUPT_MASK_LINK_UP               BIT(9)
+#define LAN9250_PHY_INTERRUPT_MASK_ENERGYON              BIT(7)
+#define LAN9250_PHY_INTERRUPT_MASK_AN_COMPLETE           BIT(6)
+#define LAN9250_PHY_INTERRUPT_MASK_REMOTE_FAULT          BIT(5)
+#define LAN9250_PHY_INTERRUPT_MASK_LINK_DOWN             BIT(4)
+#define LAN9250_PHY_INTERRUPT_MASK_AN_LP_ACK             BIT(3)
+#define LAN9250_PHY_INTERRUPT_MASK_PARALLEL_DETECT_FAULT BIT(2)
+#define LAN9250_PHY_INTERRUPT_MASK_AN_PAGE_RECEIVED      BIT(1)
+
+/* Chip ID and Revision register */
+#define LAN9250_ID_REV_CHIP_ID         0xFFFF0000
+#define LAN9250_ID_REV_CHIP_ID_DEFAULT 0x92500000
+#define LAN9250_ID_REV_CHIP_REV        0x0000FFFF
+
+struct lan9250_config {
+	struct spi_dt_spec spi;
+	struct gpio_dt_spec interrupt;
+	struct gpio_dt_spec reset;
+	uint8_t full_duplex;
+	int32_t timeout;
+};
+
+struct lan9250_runtime {
+	struct net_if *iface;
+	const struct device *dev;
+
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ETH_LAN9250_RX_THREAD_STACK_SIZE);
+	k_tid_t tid_int;
+	struct k_thread thread;
+
+	uint8_t mac_address[6];
+	struct gpio_callback gpio_cb;
+	struct k_sem tx_rx_sem;
+	struct k_sem int_sem;
+	uint8_t buf[NET_ETH_MAX_FRAME_SIZE];
+	struct k_mutex lock;
+};
+
+#endif /*_LAN9250_*/
diff --git a/dts/bindings/ethernet/microchip,lan9250.yaml b/dts/bindings/ethernet/microchip,lan9250.yaml
new file mode 100644
index 000000000000000..5f64875994474e0
--- /dev/null
+++ b/dts/bindings/ethernet/microchip,lan9250.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2024, Mario Paja
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    LAN9250 standalone 10/100BASE-T Ethernet controller with SPI interface
+
+compatible: "microchip,lan9250"
+
+include: [spi-device.yaml, ethernet-controller.yaml]
+
+properties:
+  int-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The interrupt pin of LAN9250 is active low.
+      If connected directly the MCU pin should be configured
+      as active low.