From e384105a2a3809c319f0740e2ebf6166da895fcb Mon Sep 17 00:00:00 2001
From: serge-sans-paille <serge.guelton@telecom-bretagne.eu>
Date: Tue, 15 Oct 2024 21:04:45 +0200
Subject: [PATCH] WIP

---
 include/xsimd/types/xsimd_rvv_register.hpp | 72 +++++++++++++++++++++-
 1 file changed, 71 insertions(+), 1 deletion(-)

diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
index 70d760e23..4d5258d30 100644
--- a/include/xsimd/types/xsimd_rvv_register.hpp
+++ b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -95,8 +95,10 @@ namespace xsimd
         }                                                                                 \
         template <>                                                                       \
         XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; }                    \
-        static XSIMD_INLINE byte_type as_bytes(type x) noexcept                           \
+        template <class U>                                                                \
+        static XSIMD_INLINE byte_type as_bytes(U x) noexcept                              \
         {                                                                                 \
+            static_assert(std::is_same<U, type>::value, "inconsistent conversion types"); \
             const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
             return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words);         \
         }                                                                                 \
@@ -133,6 +135,74 @@ namespace xsimd
             {
                 return __riscv_vreinterpret_i8m8(x);
             }
+            template <>
+            XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int8_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::type
+            rvv_type_info<uint16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u16m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<uint32_t, rvv_width_m1 * 1>::type
+            rvv_type_info<uint32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u32m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<uint64_t, rvv_width_m1 * 1>::type
+            rvv_type_info<uint64_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u64m1(x);
+            }
+
+            //
+
+            template <>
+            XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 8>::byte_type
+            rvv_type_info<int8_t, rvv_width_m1 * 8>::as_bytes<__rvv_int8m8_t>(__rvv_int8m8_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m8(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int8_t, rvv_width_m1 * 1>::as_bytes<__rvv_int8m1_t>(__rvv_int8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+
+            template <>
+            XSIMD_INLINE rvv_type_info<uint8_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<uint8_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint8m1_t>(__rvv_uint8m1_t x) noexcept
+            {
+                return x;
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<uint16_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint16m1_t>(__rvv_uint16m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<uint32_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<uint32_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint32m1_t>(__rvv_uint32m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<uint64_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<uint64_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint64m1_t>(__rvv_uint64m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
 
             // rvv_blob is storage-type abstraction for a vector register.
             template <class T, size_t Width>