From 632601d9be0c5cee9b069e67f180668536b2bf25 Mon Sep 17 00:00:00 2001
From: serge-sans-paille <serge.guelton@telecom-bretagne.eu>
Date: Tue, 29 Oct 2024 09:07:46 +0100
Subject: [PATCH] Force zero tail for risc-v vcompress

Fix #1060
---
 include/xsimd/arch/xsimd_rvv.hpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/xsimd/arch/xsimd_rvv.hpp b/include/xsimd/arch/xsimd_rvv.hpp
index 75f1145cd..956bd67c8 100644
--- a/include/xsimd/arch/xsimd_rvv.hpp
+++ b/include/xsimd/arch/xsimd_rvv.hpp
@@ -1129,13 +1129,14 @@ namespace xsimd
          *************/
         namespace detail
         {
-            XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress), , vec(vec, bvec))
+            XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress XSIMD_RVV_M), , vec(vec, bvec, vec))
         }
         // compress
         template <class A, class T>
         XSIMD_INLINE batch<T, A> compress(batch<T, A> const& x, batch_bool<T, A> const& mask, requires_arch<rvv>) noexcept
         {
-            return detail::rvvcompress(x, mask);
+            const auto zero = broadcast<A>(T(0), rvv {});
+            return detail::rvvcompress(x, mask, zero);
         }
 
         /***************