Mismatched address widths

[ZipCPU]

AXI addresses are octet based, WB addresses are word based. For a 32-bit data word, the AXI address should have another 2 bits beyond what the WB address would provide. This core treats the two as though they were identical.

[wallento]

Hi, you are right, but it depends on the granularity right? Currently it only supports byte granularity and not word granularity (width of sel is width of data/8). Only once it supports other granularities this should become an issue, correct?

[ZipCPU]

Thanks for checking me. I went back to the spec to double check.

It turns out this is actually an issue now. Check out p34 of the WB spec, B3, for the definition of ADR_O. Let's let SZ = the number of bytes your core can address. Then the MSB would reflect $clog2(SZ)-1. So, for a 64kB address, the MSB would be 15. The LSB on the other hand is determined by the granularity. For a core with a 32-bit data bus with 8-bit granularity (such as you've built here), the LSB is bit 2.

Since not all tools support a non-zero LSB, I can understand setting the LSB to zero. (I do it all the time.) However, if you do that then the width needs to be 16-2 bits, or [13:0], for a 64kB memory on a 32-bit data width bus.

You can also see an example of this in the simple 16-bit slave on page 111 o fthe WB spec, B3. In that example, the address has already been used to select the two bytes of that core.

This is actually a good rule to follow. If you break spec (as you currently are), then you break the AXI interface too. According to AXI, if you have an address of 1, then the lowest strobe line must be zero. For an AXI address of 2, the lowest two strobe lines must be zero, etc. WB has no such requirement.

The good news is that, depending on how the rest of your core was accessing memory, you might quadruple the memory available to you by this simple change.