diff --git a/pcileech/Android.mk b/pcileech/Android.mk
index 626397b..18ee256 100644
--- a/pcileech/Android.mk
+++ b/pcileech/Android.mk
@@ -14,7 +14,7 @@ LOCAL_CFLAGS := -D ANDROID
 LOCAL_LDLIBS := -L$(LOCAL_PATH)/lib -llog -g
 
 LOCAL_C_INCLUDES := bionic
-LOCAL_SRC_FILES:= pcileech.c oscompatibility.c device.c device3380.c device605_601.c device605_tcp.c executor.c extra.c help.c kmd.c memdump.c mempatch.c statistics.c tlp.c util.c vfs.c
+LOCAL_SRC_FILES:= pcileech.c oscompatibility.c device.c device3380.c devicefpga.c device605_tcp.c executor.c extra.c help.c kmd.c memdump.c mempatch.c statistics.c tlp.c util.c vfs.c
 
 LOCAL_MODULE := pcileech
 LOCAL_SHARED_LIBRARIES += libusb1.0
diff --git a/pcileech/Makefile b/pcileech/Makefile
index b6eb9c8..bd01240 100644
--- a/pcileech/Makefile
+++ b/pcileech/Makefile
@@ -1,7 +1,7 @@
 CC=gcc
 CFLAGS=-I. -D LINUX -pthread `pkg-config libusb-1.0 --libs --cflags`
 DEPS = pcileech.h
-OBJ = pcileech oscompatibility.o pcileech.o device.o device3380.o device605_601.o device605_tcp.o executor.o extra.o help.o kmd.o memdump.o mempatch.o statistics.o tlp.o util.o vfs.o
+OBJ = pcileech oscompatibility.o pcileech.o device.o device3380.o devicefpga.o device605_tcp.o executor.o extra.o help.o kmd.o memdump.o mempatch.o statistics.o tlp.o util.o vfs.o
 
 %.o: %.c $(DEPS)
 	$(CC) -c -o $@ $< $(CFLAGS)
diff --git a/pcileech/device.c b/pcileech/device.c
index 0eacdd6..36ee6bb 100644
--- a/pcileech/device.c
+++ b/pcileech/device.c
@@ -1,13 +1,13 @@
 // device.c : implementation related to hardware devices.
 //
-// (c) Ulf Frisk, 2016, 2017
+// (c) Ulf Frisk, 2016-2018
 // Author: Ulf Frisk, pcileech@frizk.net
 //
 #include "device.h"
 #include "kmd.h"
 #include "statistics.h"
 #include "device3380.h"
-#include "device605_601.h"
+#include "devicefpga.h"
 #include "device605_tcp.h"
 
 typedef struct tdREAD_DMA_EX_MEMORY_MAP {
@@ -58,6 +58,7 @@ DWORD DeviceReadDMAEx_DoWork(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _
 			DeviceReadDMAEx_IsMemoryMapOK(pMemoryMap, qwAddr + cbRdOff, cbRd) &&
 			DeviceReadDMA(ctx, qwAddr + cbRdOff, pb + cbRdOff, cbRd, 0);
 		if(!result && !pMemoryMap->fProbeExecuted && ctx->cfg->dev.pfnProbeDMA) { // probe memory on 1st fail (if supported)
+            memset(pMemoryMap->pb, 0, pMemoryMap->cPages);
 			DeviceProbeDMA(ctx, pMemoryMap->qwAddrBase, pMemoryMap->cPages, pMemoryMap->pb);
 			pMemoryMap->fProbeExecuted = TRUE;
 		}
@@ -121,7 +122,7 @@ BOOL DeviceWriteDMA(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ PBYTE
 	return result;
 }
 
-BOOL DeviceProbeDMA(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ DWORD cPages, _Out_ __bcount(cPages) PBYTE pbResultMap)
+BOOL DeviceProbeDMA(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ DWORD cPages, _Inout_ __bcount(cPages) PBYTE pbResultMap)
 {
 	if(!ctx->cfg->dev.pfnProbeDMA) { return FALSE; }
 	ctx->cfg->dev.pfnProbeDMA(ctx, qwAddr, cPages, pbResultMap);
@@ -153,8 +154,8 @@ BOOL DeviceOpen(_Inout_ PPCILEECH_CONTEXT ctx)
 	if(PCILEECH_DEVICE_USB3380 == ctx->cfg->dev.tp || PCILEECH_DEVICE_NA == ctx->cfg->dev.tp) {
 		result = Device3380_Open(ctx);
 	}
-	if(PCILEECH_DEVICE_SP605_FT601 == ctx->cfg->dev.tp || PCILEECH_DEVICE_NA == ctx->cfg->dev.tp) {
-		result = Device605_601_Open(ctx);
+	if(PCILEECH_DEVICE_FPGA == ctx->cfg->dev.tp || PCILEECH_DEVICE_NA == ctx->cfg->dev.tp) {
+		result = DeviceFPGA_Open(ctx);
 	}
 	if(PCILEECH_DEVICE_SP605_TCP == ctx->cfg->dev.tp) {
 		result = Device605_TCP_Open(ctx);
diff --git a/pcileech/device.h b/pcileech/device.h
index c9007e6..13a586f 100644
--- a/pcileech/device.h
+++ b/pcileech/device.h
@@ -71,9 +71,11 @@ BOOL DeviceWriteDMA(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ PBYTE
 * -- qwAddr = address to start probe from.
 * -- cPages = number of 4kB pages to probe.
 * -- pbResultMap = result map, 1 byte represents 1 page, 0 = fail, 1 = success.
+*       (individual page elements in pbResultMap must be set to 0 [fail] on call
+*       for probe to take place on individual page).
 * -- return = FALSE if not supported by underlying hardware, TRUE if supported.
 */
-BOOL DeviceProbeDMA(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ DWORD cPages, _Out_ __bcount(cPages) PBYTE pbResultMap);
+BOOL DeviceProbeDMA(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ DWORD cPages, _Inout_ __bcount(cPages) PBYTE pbResultMap);
 
 /*
 * Write target physical memory. If an KMD is inserted in the target kernel the
diff --git a/pcileech/device605_601.c b/pcileech/device605_601.c
deleted file mode 100644
index 440c61e..0000000
--- a/pcileech/device605_601.c
+++ /dev/null
@@ -1,517 +0,0 @@
-// device605_601.c : implementation related to the Xilinx SP605 dev board flashed with bitstream for FTDI UMFT601X-B addon-board.
-//
-// (c) Ulf Frisk, 2017
-// Author: Ulf Frisk, pcileech@frizk.net
-//
-#ifdef WIN32
-
-#include "device605_601.h"
-#include "device.h"
-#include "tlp.h"
-#include "util.h"
-
-//-------------------------------------------------------------------------------
-// FPGA/SP605/FT601 defines below.
-//-------------------------------------------------------------------------------
-
-#define FPGA_TLP_TX_VALID				0x77000000
-#define FPGA_TLP_TX_VALID_LAST			0x77040000
-#define FPGA_LOOP_TX_VALID     			0x77020000
-
-#define SP605_601_PROBE_MAXPAGES		0x400
-#define SP605_601_MAX_SIZE_RX			0x0001f000	// in data bytes (excl. overhead/TLP headers)
-#define SP605_601_MAX_SIZE_TX			0x00002000  // in total data (incl. overhead/TLP headers)
-
-#define FPGA_CMD_VERSION				0x01
-#define FPGA_CMD_PCIE_STATUS			0x02
-
-#define ENDIAN_SWAP_WORD(x)		(x = (x << 8) | (x >> 8))
-#define ENDIAN_SWAP_DWORD(x)	(x = (x << 24) | ((x >> 8) & 0xff00) | ((x << 8) & 0xff0000) | (x >> 24))
-
-// Delay in uS. DELAY_READ=300, DELAY_WRITE=150 -> 85MB/s.
-// Values below are a bit more conservative for hw tolerance reasons.
-#define DELAY_READ_DEFAULT				400
-#define DELAY_WRITE_DEFAULT				175
-#define DELAY_PROBE_DEFAULT				500
-
-typedef struct tdDEVICE_CONTEXT_SP605_601 {
-	WORD wDeviceId;
-	WORD wFpgaVersion;
-	WORD wFpgaStatus;
-	BOOL isPrintTlp;
-	PTLP_CALLBACK_BUF_MRd pMRdBuffer;
-	struct {
-		PBYTE pb;
-		DWORD cb;
-		DWORD cbMax;
-	} rxbuf;
-	struct {
-		PBYTE pb;
-		DWORD cb;
-		DWORD cbMax;
-	} txbuf;
-	struct {
-		HMODULE hModule;
-		HANDLE hFTDI;
-		ULONG(*pfnFT_Create)(
-			PVOID pvArg,
-			DWORD dwFlags,
-			HANDLE *pftHandle
-		);
-		ULONG(*pfnFT_Close)(
-			HANDLE ftHandle
-		);
-		ULONG(*pfnFT_WritePipe)(
-			HANDLE ftHandle,
-			UCHAR ucPipeID,
-			PUCHAR pucBuffer,
-			ULONG ulBufferLength,
-			PULONG pulBytesTransferred,
-			LPOVERLAPPED pOverlapped
-		);
-		ULONG(*pfnFT_ReadPipe)(
-			HANDLE ftHandle,
-			UCHAR ucPipeID,
-			PUCHAR pucBuffer,
-			ULONG ulBufferLength,
-			PULONG pulBytesTransferred,
-			LPOVERLAPPED pOverlapped
-		);
-		ULONG(*pfnFT_AbortPipe)(
-			HANDLE ftHandle,
-			UCHAR ucPipeID
-		);
-
-	} dev;
-	BOOL(*hRxTlpCallbackFn)(_Inout_ PTLP_CALLBACK_BUF_MRd pBufferMrd, _In_ PBYTE pb, _In_ DWORD cb, _In_opt_ HANDLE hEventCompleted);
-	DWORD DELAY_READ;
-	DWORD DELAY_WRITE;
-	DWORD DELAY_PROBE;
-} DEVICE_CONTEXT_SP605_601, *PDEVICE_CONTEXT_SP605_601;
-
-//-------------------------------------------------------------------------------
-// FPGA/SP605/FT601 implementation below.
-//-------------------------------------------------------------------------------
-
-VOID Device601_601_InitializeFTDI(_In_ PDEVICE_CONTEXT_SP605_601 ctx)
-{
-	DWORD status;
-	// Load FTDI Library
-	ctx->dev.hModule = LoadLibrary(L"FTD3XX.dll");
-	if(!ctx->dev.hModule) { return; }
-	ctx->dev.pfnFT_AbortPipe = (ULONG(*)(HANDLE, UCHAR))
-		GetProcAddress(ctx->dev.hModule, "FT_AbortPipe");
-	ctx->dev.pfnFT_Close = (ULONG(*)(HANDLE))
-		GetProcAddress(ctx->dev.hModule, "FT_Close");
-	ctx->dev.pfnFT_Create = (ULONG(*)(PVOID, DWORD, HANDLE*))
-		GetProcAddress(ctx->dev.hModule, "FT_Create");
-	ctx->dev.pfnFT_ReadPipe = (ULONG(*)(HANDLE, UCHAR, PUCHAR, ULONG, PULONG, LPOVERLAPPED))
-		GetProcAddress(ctx->dev.hModule, "FT_ReadPipe");
-	ctx->dev.pfnFT_WritePipe = (ULONG(*)(HANDLE, UCHAR, PUCHAR, ULONG, PULONG, LPOVERLAPPED))
-		GetProcAddress(ctx->dev.hModule, "FT_WritePipe");
-	// Open FTDI
-	status = ctx->dev.pfnFT_Create(NULL, 0x10 /*FT_OPEN_BY_INDEX*/, &ctx->dev.hFTDI);
-	if(status || !ctx->dev.hFTDI) { return; }
-	ctx->dev.pfnFT_AbortPipe(ctx->dev.hFTDI, 0x02);
-	ctx->dev.pfnFT_AbortPipe(ctx->dev.hFTDI, 0x82);
-}
-
-VOID Device605_601_Close(_Inout_ PPCILEECH_CONTEXT ctxPcileech)
-{
-	PDEVICE_CONTEXT_SP605_601 ctx = (PDEVICE_CONTEXT_SP605_601)ctxPcileech->hDevice;
-	if(!ctx) { return; }
-	if(ctx->dev.hFTDI) { ctx->dev.pfnFT_Close(ctx->dev.hFTDI); }
-	if(ctx->dev.hModule) { FreeLibrary(ctx->dev.hModule); }
-	if(ctx->rxbuf.pb) { LocalFree(ctx->rxbuf.pb); }
-	if(ctx->txbuf.pb) { LocalFree(ctx->txbuf.pb); }
-	LocalFree(ctx);
-	ctxPcileech->hDevice = 0;
-}
-
-VOID Device605_601_GetDeviceID_FpgaVersion(_In_ PDEVICE_CONTEXT_SP605_601 ctx)
-{
-	DWORD status;
-	DWORD cbTX, cbRX, i, j;
-	PBYTE pbRX = LocalAlloc(0, 0x01000000);
-	DWORD dwStatus, dwData, cdwCfg = 0;
-	PDWORD pdwData;
-	BYTE pbTX[24] = {
-		// cfg read addr 0
-		0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x01, 0x77,
-		// cmd msg: version
-		0x00, 0x00, 0x00, 0x00,  0x01, 0x00, 0x03, 0x77,
-		// cmd msg: PCIe status
-		0x00, 0x00, 0x00, 0x00,  0x02, 0x00, 0x03, 0x77
-	};
-	status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, pbTX, 24, &cbTX, NULL);
-	if(status) { goto fail; }
-	status = ctx->dev.pfnFT_ReadPipe(ctx->dev.hFTDI, 0x82, pbRX, 0x01000000, &cbRX, NULL);
-	if(status) { goto fail; }
-	for(i = 0; i < cbRX; i += 32) {
-		dwStatus = *(PDWORD)(pbRX + i);
-		pdwData = (PDWORD)(pbRX + i + 4);
-		if((dwStatus & 0xf0000000) != 0xe0000000) { continue; }
-		for(j = 0; j < 7; j++) {
-			dwData = *pdwData;
-			if((dwStatus & 0x03) == 0x03) { // CMD REPLY (or filler)
-				if((dwData >> 24) == FPGA_CMD_VERSION) { // FPGA bitstream version
-					ctx->wFpgaVersion = (WORD)dwData;
-				}
-				if((dwData >> 24) == FPGA_CMD_PCIE_STATUS) { // PCIe status
-					ctx->wFpgaStatus = (WORD)dwData;
-				}
-			}
-			if((dwStatus & 0x03) == 0x01) { // PCIe CFG REPLY
-				if(((++cdwCfg % 2) == 0) && (WORD)dwData) {	// DeviceID
-					ctx->wDeviceId = (WORD)dwData;
-				}
-			}
-			pdwData++;
-			dwStatus >>= 4;
-		}
-	}
-fail:
-	LocalFree(pbRX);
-}
-
-BOOL Device605_601_TxTlp(_In_ PDEVICE_CONTEXT_SP605_601 ctx, _In_ PBYTE pbTlp, _In_ DWORD cbTlp, BOOL fRdKeepalive, BOOL fFlush)
-{
-	DWORD status;
-	PBYTE pbTx;
-	DWORD i, cbTx, cbTxed = 0;
-	if(cbTlp & 0x3) { return FALSE; }
-	if(cbTlp > 2048) { return FALSE; }
-	if(ctx->isPrintTlp) {
-		TLP_Print(pbTlp, cbTlp, TRUE);
-	}
-	// prepare transmit buffer
-	pbTx = ctx->txbuf.pb + ctx->txbuf.cb;
-	cbTx = 2 * cbTlp;
-	for(i = 0; i < cbTlp; i += 4) {
-		*(PDWORD)(pbTx + (i << 1)) = *(PDWORD)(pbTlp + i);
-		*(PDWORD)(pbTx + ((i << 1) + 4)) = FPGA_TLP_TX_VALID;
-	} 
-	if(cbTlp) {
-		*(PDWORD)(pbTx + ((i << 1) - 4)) = FPGA_TLP_TX_VALID_LAST;
-	}
-	if(fRdKeepalive) {
-		cbTx += 8;
-		*(PDWORD)(pbTx + (i << 1)) = 0xffeeddcc;
-		*(PDWORD)(pbTx + ((i << 1) + 4)) = FPGA_LOOP_TX_VALID;
-	}
-	ctx->txbuf.cb += cbTx;
-	// transmit
-	if((ctx->txbuf.cb > SP605_601_MAX_SIZE_TX) || (fFlush && ctx->txbuf.cb)) {
-		status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, ctx->txbuf.pb, ctx->txbuf.cb, &cbTxed, NULL);
-		ctx->txbuf.cb = 0;
-		return (0 == status);
-	}
-	return TRUE;
-}
-
-#define TLP_RX_MAX_SIZE		1024
-VOID Device605_601_RxTlpSynchronous(_In_ PDEVICE_CONTEXT_SP605_601 ctx)
-{
-	DWORD status;
-	DWORD i, j, cdwTlp = 0;
-	BYTE pbTlp[TLP_RX_MAX_SIZE];
-	PDWORD pdwTlp = (PDWORD)pbTlp;
-	PDWORD pdwRx = (PDWORD)ctx->rxbuf.pb;
-	DWORD dwStatus, *pdwData;
-	status = ctx->dev.pfnFT_ReadPipe(ctx->dev.hFTDI, 0x82, ctx->rxbuf.pb, ctx->rxbuf.cbMax, &ctx->rxbuf.cb, NULL);
-	if(status) {
-		ctx->dev.pfnFT_AbortPipe(ctx->dev.hFTDI, 0x82);
-		return;
-	}
-	for(i = 0; i < ctx->rxbuf.cb; i += 32) { // index in 64-bit (QWORD)
-		dwStatus = *(PDWORD)(ctx->rxbuf.pb + i);
-		pdwData = (PDWORD)(ctx->rxbuf.pb + i + 4);
-		if((dwStatus & 0xf0000000) != 0xe0000000) { continue; }
-		for(j = 0; j < 7; j++) {
-			if((dwStatus & 0x03) == 0x00) { // PCIe TLP
-				pdwTlp[cdwTlp] = *pdwData;
-				cdwTlp++;
-				if(cdwTlp >= TLP_RX_MAX_SIZE / sizeof(DWORD)) { return; }
-			}
-			if((dwStatus & 0x07) == 0x04) { // PCIe TLP and LAST
-				if(cdwTlp >= 3) {
-					if(ctx->isPrintTlp) {
-						TLP_Print(pbTlp, cdwTlp << 2, FALSE);
-					}
-					if(ctx->hRxTlpCallbackFn) {
-						ctx->hRxTlpCallbackFn(ctx->pMRdBuffer, pbTlp, cdwTlp << 2, NULL);
-					}
-				} else {
-					printf("Device Info: SP605 / FT601: Bad PCIe TLP received! Should not happen!\n");
-				}
-				cdwTlp = 0;
-			}
-			pdwData++;
-			dwStatus >>= 4;
-		}
-	}
-}
-
-BOOL Device605_601_ReadDMA(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwAddr, _Out_ PBYTE pb, _In_ DWORD cb)
-{
-	PDEVICE_CONTEXT_SP605_601 ctx = (PDEVICE_CONTEXT_SP605_601)ctxPcileech->hDevice;
-	TLP_CALLBACK_BUF_MRd rxbuf;
-	DWORD tx[4], o, i;
-	BOOL is32, isFlush;
-	PTLP_HDR_MRdWr64 hdrRd64 = (PTLP_HDR_MRdWr64)tx;
-	PTLP_HDR_MRdWr32 hdrRd32 = (PTLP_HDR_MRdWr32)tx;
-	if(cb > SP605_601_MAX_SIZE_RX) { return FALSE; }
-	if(qwAddr % 0x1000) { return FALSE; }
-	if((cb >= 0x1000) && (cb % 0x1000)) { return FALSE; }
-	if((cb < 0x1000) && (cb % 0x8)) { return FALSE; }
-	// prepare
-	rxbuf.cb = 0;
-	rxbuf.pb = pb;
-	rxbuf.cbMax = cb;
-	ctx->pMRdBuffer = &rxbuf;
-	ctx->hRxTlpCallbackFn = TLP_CallbackMRd;
-	// transmit TLPs
-	for(o = 0; o < cb; o += 0x1000) {
-		memset(tx, 0, 16);
-		is32 = qwAddr + o < 0x100000000;
-		if(is32) {
-			hdrRd32->h.TypeFmt = TLP_MRd32;
-			hdrRd32->h.Length = (WORD)((cb < 0x1000) ? cb >> 2 : 0);
-			hdrRd32->RequesterID = ctx->wDeviceId;
-			hdrRd32->Tag = (BYTE)(o >> 12);
-			hdrRd32->FirstBE = 0xf;
-			hdrRd32->LastBE = 0xf;
-			hdrRd32->Address = (DWORD)(qwAddr + o);
-		} else {
-			hdrRd64->h.TypeFmt = TLP_MRd64;
-			hdrRd64->h.Length = (WORD)((cb < 0x1000) ? cb >> 2 : 0);
-			hdrRd64->RequesterID = ctx->wDeviceId;
-			hdrRd64->Tag = (BYTE)(o >> 12);
-			hdrRd64->FirstBE = 0xf;
-			hdrRd64->LastBE = 0xf;
-			hdrRd64->AddressHigh = (DWORD)((qwAddr + o) >> 32);
-			hdrRd64->AddressLow = (DWORD)(qwAddr + o);
-		}
-		for(i = 0; i < 4; i++) {
-			ENDIAN_SWAP_DWORD(tx[i]);
-		}
-		isFlush = ((o % 0x8000) == 0x7000);
-		if(isFlush) {
-			Device605_601_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, TRUE);
-			usleep(ctx->DELAY_WRITE);
-		} else {
-			Device605_601_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, FALSE);
-		}
-	}
-	Device605_601_TxTlp(ctx, NULL, 0, TRUE, TRUE);
-	usleep(ctx->DELAY_READ);
-	Device605_601_RxTlpSynchronous(ctx);
-	ctx->pMRdBuffer = NULL;
-	return rxbuf.cb >= rxbuf.cbMax;
-}
-
-VOID Device605_601_ProbeDMA(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwAddr, _In_ DWORD cPages, _Out_ __bcount(cPages) PBYTE pbResultMap)
-{
-	DWORD i, j;
-	PDEVICE_CONTEXT_SP605_601 ctx = (PDEVICE_CONTEXT_SP605_601)ctxPcileech->hDevice;
-	TLP_CALLBACK_BUF_MRd bufMRd;
-	DWORD tx[4];
-	BOOL is32;
-	PTLP_HDR_MRdWr64 hdrRd64 = (PTLP_HDR_MRdWr64)tx;
-	PTLP_HDR_MRdWr32 hdrRd32 = (PTLP_HDR_MRdWr32)tx;
-	// split probe into processing chunks if too large...
-	while(cPages > SP605_601_PROBE_MAXPAGES) {
-		Device605_601_ProbeDMA(ctxPcileech, qwAddr, SP605_601_PROBE_MAXPAGES, pbResultMap);
-		cPages -= SP605_601_PROBE_MAXPAGES;
-		pbResultMap += SP605_601_PROBE_MAXPAGES;
-		qwAddr += SP605_601_PROBE_MAXPAGES << 12;
-	}
-	memset(pbResultMap, 0, cPages);
-	// prepare
-	bufMRd.cb = 0;
-	bufMRd.pb = pbResultMap;
-	bufMRd.cbMax = cPages;
-	ctx->pMRdBuffer = &bufMRd;
-	ctx->hRxTlpCallbackFn = TLP_CallbackMRdProbe;
-	// transmit TLPs
-	for(i = 0; i < cPages; i++) {
-		memset(tx, 0, 16);
-		is32 = qwAddr + (i << 12) < 0x100000000;
-		if(is32) {
-			hdrRd32->h.TypeFmt = TLP_MRd32;
-			hdrRd32->h.Length = 1;
-			hdrRd32->RequesterID = ctx->wDeviceId;
-			hdrRd32->FirstBE = 0xf;
-			hdrRd32->LastBE = 0;
-			hdrRd32->Address = (DWORD)(qwAddr + (i << 12) + ((i & 0x1f) << 2)); // 5 low address bits coded into the dword read.
-			hdrRd32->Tag = (BYTE)((i >> 5) & 0x1f); // 5 high address bits coded into tag.
-		} else {
-			hdrRd64->h.TypeFmt = TLP_MRd64;
-			hdrRd64->h.Length = 1;
-			hdrRd64->RequesterID = ctx->wDeviceId;
-			hdrRd64->FirstBE = 0xf;
-			hdrRd64->LastBE = 0;
-			hdrRd64->AddressHigh = (DWORD)((qwAddr + (i << 12)) >> 32);
-			hdrRd64->AddressLow = (DWORD)(qwAddr + (i << 12) + ((i & 0x1f) << 2)); // 5 low address bits coded into the dword read.
-			hdrRd64->Tag = (BYTE)((i >> 5) & 0x1f); // 5 high address bits coded into tag.
-		}
-		for(j = 0; j < 4; j++) {
-			ENDIAN_SWAP_DWORD(tx[j]);
-		}
-		Device605_601_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, (i % 24 == 0));
-	}
-	Device605_601_TxTlp(ctx, NULL, 0, TRUE, TRUE);
-	usleep(ctx->DELAY_PROBE);
-	Device605_601_RxTlpSynchronous(ctx);
-	ctx->hRxTlpCallbackFn = NULL;
-	ctx->pMRdBuffer = NULL;
-}
-
-// write max 128 byte packets.
-BOOL Device605_601_WriteDMA_TXP(_Inout_ PDEVICE_CONTEXT_SP605_601 ctx, _In_ QWORD qwA, _In_ BYTE bFirstBE, _In_ BYTE bLastBE, _In_ PBYTE pb, _In_ DWORD cb)
-{
-	DWORD txbuf[36], i, cbTlp;
-	PBYTE pbTlp = (PBYTE)txbuf;
-	PTLP_HDR_MRdWr32 hdrWr32 = (PTLP_HDR_MRdWr32)txbuf;
-	PTLP_HDR_MRdWr64 hdrWr64 = (PTLP_HDR_MRdWr64)txbuf;
-	memset(pbTlp, 0, 16);
-	if(qwA < 0x100000000) {
-		hdrWr32->h.TypeFmt = TLP_MWr32;
-		hdrWr32->h.Length = (WORD)(cb + 3) >> 2;
-		hdrWr32->FirstBE = bFirstBE;
-		hdrWr32->LastBE = bLastBE;
-		hdrWr32->RequesterID = ctx->wDeviceId;
-		hdrWr32->Address = (DWORD)qwA;
-		for(i = 0; i < 3; i++) {
-			ENDIAN_SWAP_DWORD(txbuf[i]);
-		}
-		memcpy(pbTlp + 12, pb, cb);
-		cbTlp = (12 + cb + 3) & ~0x3;
-	} else {
-		hdrWr64->h.TypeFmt = TLP_MWr64;
-		hdrWr64->h.Length = (WORD)(cb + 3) >> 2;
-		hdrWr64->FirstBE = bFirstBE;
-		hdrWr64->LastBE = bLastBE;
-		hdrWr64->RequesterID = ctx->wDeviceId;
-		hdrWr64->AddressHigh = (DWORD)(qwA >> 32);
-		hdrWr64->AddressLow = (DWORD)qwA;
-		for(i = 0; i < 4; i++) {
-			ENDIAN_SWAP_DWORD(txbuf[i]);
-		}
-		memcpy(pbTlp + 16, pb, cb);
-		cbTlp = (16 + cb + 3) & ~0x3;
-	}
-	return Device605_601_TxTlp(ctx, pbTlp, cbTlp, FALSE, FALSE);
-}
-
-BOOL Device605_601_WriteDMA(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwA, _In_ PBYTE pb, _In_ DWORD cb)
-{
-	PDEVICE_CONTEXT_SP605_601 ctx = (PDEVICE_CONTEXT_SP605_601)ctxPcileech->hDevice;
-	BOOL result = TRUE;
-	BYTE be, pbb[4];
-	DWORD cbtx;
-	// TX 1st dword if not aligned
-	if(cb && (qwA & 0x3)) {
-		be = (cb < 3) ? (0xf >> (4 - cb)) : 0xf;
-		be <<= qwA & 0x3;
-		cbtx = min(cb, 4 - (qwA & 0x3));
-		memcpy(pbb + (qwA & 0x3), pb, cbtx);
-		result = Device605_601_WriteDMA_TXP(ctx, qwA & ~0x3, be, 0, pbb, 4);
-		pb += cbtx;
-		cb -= cbtx;
-		qwA += cbtx;
-	}
-	// TX as 128-byte packets (aligned to 128-byte boundaries)
-	while(result && cb) {
-		cbtx = min(128 - (qwA & 0x7f), cb);
-		be = (cbtx & 0x3) ? (0xf >> (4 - (cbtx & 0x3))) : 0xf;
-		result = (cbtx <= 4) ?
-			Device605_601_WriteDMA_TXP(ctx, qwA, be, 0, pb, 4) :
-			Device605_601_WriteDMA_TXP(ctx, qwA, 0xf, be, pb, cbtx);
-		pb += cbtx;
-		cb -= cbtx;
-		qwA += cbtx;
-	}
-	return Device605_601_TxTlp(ctx, NULL, 0, FALSE, TRUE) && result; // Flush and Return.
-}
-
-BOOL Device605_601_ListenTlp(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ DWORD dwTime)
-{
-	PDEVICE_CONTEXT_SP605_601 ctx = (PDEVICE_CONTEXT_SP605_601)ctxPcileech->hDevice;
-	QWORD tmStart = GetTickCount64();
-	while(GetTickCount64() - tmStart < dwTime) {
-		Device605_601_TxTlp(ctx, NULL, 0, TRUE, TRUE);
-		Sleep(10);
-		Device605_601_RxTlpSynchronous(ctx);
-	}
-	return TRUE;
-}
-
-BOOL Device605_601_WriteTlp(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ PBYTE pbTlp, _In_ DWORD cbTlp)
-{
-	PDEVICE_CONTEXT_SP605_601 ctx = (PDEVICE_CONTEXT_SP605_601)ctxPcileech->hDevice;
-	return Device605_601_TxTlp(ctx, pbTlp, cbTlp, FALSE, TRUE);
-}
-
-BOOL Device605_601_Open(_Inout_ PPCILEECH_CONTEXT ctxPcileech)
-{
-	PDEVICE_CONTEXT_SP605_601 ctx;
-	ctx = LocalAlloc(LMEM_ZEROINIT, sizeof(DEVICE_CONTEXT_SP605_601));
-	if(!ctx) { return FALSE; }
-	ctxPcileech->hDevice = (HANDLE)ctx;
-	Device601_601_InitializeFTDI(ctx);
-	if(!ctx->dev.hModule && ctxPcileech->cfg->fVerbose) { printf("Device Info: SP605 / FT601: Could not load FTD3XX.dll.\n"); }
-	if(!ctx->dev.hModule) { goto fail; }
-	if(!ctx->dev.hFTDI && ctxPcileech->cfg->fVerbose) { printf("Device Info: SP605 / FT601: Could not connect to device.\n"); }
-	if(!ctx->dev.hFTDI) { goto fail; }
-	Device605_601_GetDeviceID_FpgaVersion(ctx);
-	if(!ctx->wDeviceId) { goto fail; }
-	ctx->rxbuf.cbMax = (DWORD)(1.25 * SP605_601_MAX_SIZE_RX + 0x1000);  // buffer size tuned to lowest possible (+margin) for performance.
-	ctx->rxbuf.pb = LocalAlloc(0, ctx->rxbuf.cbMax);
-	if(!ctx->rxbuf.pb) { goto fail; }
-	ctx->txbuf.cbMax = SP605_601_MAX_SIZE_TX + 0x10000;
-	ctx->txbuf.pb = LocalAlloc(0, ctx->txbuf.cbMax);
-	if(!ctx->txbuf.pb) { goto fail; }
-	ctx->isPrintTlp = ctxPcileech->cfg->fVerboseExtra;
-	ctx->DELAY_READ = ctxPcileech->cfg->qwDeviceOpt[0] ? (DWORD)ctxPcileech->cfg->qwDeviceOpt[0] : DELAY_READ_DEFAULT;
-	ctx->DELAY_WRITE = ctxPcileech->cfg->qwDeviceOpt[1] ? (DWORD)ctxPcileech->cfg->qwDeviceOpt[1] : DELAY_WRITE_DEFAULT;
-	ctx->DELAY_PROBE = ctxPcileech->cfg->qwDeviceOpt[2] ? (DWORD)ctxPcileech->cfg->qwDeviceOpt[2] : DELAY_PROBE_DEFAULT;
-	// set callback functions and fix up config
-	ctxPcileech->cfg->dev.tp = PCILEECH_DEVICE_SP605_FT601;
-	ctxPcileech->cfg->dev.qwMaxSizeDmaIo = SP605_601_MAX_SIZE_RX;
-	ctxPcileech->cfg->dev.qwAddrMaxNative = 0x0000ffffffffffff;
-	ctxPcileech->cfg->dev.fPartialPageReadSupported = TRUE;
-	ctxPcileech->cfg->dev.pfnClose = Device605_601_Close;
-	ctxPcileech->cfg->dev.pfnProbeDMA = Device605_601_ProbeDMA;
-	ctxPcileech->cfg->dev.pfnReadDMA = Device605_601_ReadDMA;
-	ctxPcileech->cfg->dev.pfnWriteDMA = Device605_601_WriteDMA;
-	ctxPcileech->cfg->dev.pfnWriteTlp = Device605_601_WriteTlp;
-	ctxPcileech->cfg->dev.pfnListenTlp = Device605_601_ListenTlp;
-	// return
-	if(ctxPcileech->cfg->fVerbose) { 
-		if((ctx->DELAY_READ != DELAY_READ_DEFAULT) || (ctx->DELAY_WRITE != DELAY_WRITE_DEFAULT) || (ctx->DELAY_PROBE != DELAY_PROBE_DEFAULT)) {
-			printf("Device Info: SP605 / FT601 [%i,%i,%i]\n", ctx->DELAY_READ, ctx->DELAY_WRITE, ctx->DELAY_PROBE);
-		} else {
-			printf("Device Info: SP605 / FT601.\n");
-		}
-	}
-	return TRUE;
-fail:
-	Device605_601_Close(ctxPcileech);
-	return FALSE;
-}
-
-#endif /* WIN32 */
-#if defined(LINUX) || defined(ANDROID)
-
-#include "device605_601.h"
-
-BOOL Device605_601_Open(_Inout_ PPCILEECH_CONTEXT ctx)
-{
-	if(ctx->cfg->dev.tp == PCILEECH_DEVICE_SP605_FT601) {
-		printf("SP605 / FT601: Failed. Device currently only supported in PCILeech for Windows.");
-	}
-	return FALSE;
-}
-
-#endif /* LINUX || ANDROID */
diff --git a/pcileech/device605_601.h b/pcileech/device605_601.h
deleted file mode 100644
index cf730be..0000000
--- a/pcileech/device605_601.h
+++ /dev/null
@@ -1,17 +0,0 @@
-// device605_601.h : definitions related to the Xilinx SP605 dev board flashed with bitstream for FTDI UMFT601X-B addon-board.
-//
-// (c) Ulf Frisk, 2017
-// Author: Ulf Frisk, pcileech@frizk.net
-//
-#ifndef __DEVICE605_601_H__
-#define __DEVICE605_601_H__
-#include "pcileech.h"
-
-/*
-* Open a connection to the SP605/FT601 PCILeech flashed device.
-* -- ctx
-* -- result
-*/
-BOOL Device605_601_Open(_Inout_ PPCILEECH_CONTEXT ctx);
-
-#endif /* __DEVICE605_601_H__ */
diff --git a/pcileech/devicefpga.c b/pcileech/devicefpga.c
new file mode 100644
index 0000000..b635325
--- /dev/null
+++ b/pcileech/devicefpga.c
@@ -0,0 +1,835 @@
+// devicefpga.h : implementation related to the:
+//     - Xilinx SP605 dev board flashed with PCILeech bitstream and FTDI UMFT601X-B addon-board.
+//     - Xilinx AC701 dev board flashed with PCILeech bitstream and FTDI UMFT601X-B addon-board.
+//     - PCIeScreamer board flashed with PCILeech bitstream.
+//
+// (c) Ulf Frisk, 2017-2018
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+#ifdef WIN32
+
+#include "devicefpga.h"
+#include "device.h"
+#include "tlp.h"
+#include "util.h"
+
+//-------------------------------------------------------------------------------
+// FPGA defines below.
+//-------------------------------------------------------------------------------
+
+#define FPGA_CMD_VERSION        0x01
+#define FPGA_CMD_ID             0x03
+
+#define ENDIAN_SWAP_WORD(x)     (x = (x << 8) | (x >> 8))
+#define ENDIAN_SWAP_DWORD(x)    (x = (x << 24) | ((x >> 8) & 0xff00) | ((x << 8) & 0xff0000) | (x >> 24))
+
+typedef struct tdDEV_CFG_PHY {
+    BYTE magic;
+    BYTE tp_cfg : 4;
+    BYTE tp : 4;
+    struct {
+        BYTE pl_directed_link_auton : 1;
+        BYTE pl_directed_link_change : 2;
+        BYTE pl_directed_link_speed : 1;
+        BYTE pl_directed_link_width : 2;
+        BYTE pl_upstream_prefer_deemph : 1;
+        BYTE pl_transmit_hot_rst : 1;
+        BYTE pl_downstream_deemph_source : 1;
+        BYTE _filler : 7;
+    } wr;
+    struct {
+        BYTE pl_ltssm_state : 6;
+        BYTE pl_rx_pm_state : 2;
+        BYTE pl_tx_pm_state : 3;
+        BYTE pl_initial_link_width : 3;
+        BYTE pl_lane_reversal_mode : 2;
+        BYTE pl_sel_lnk_width : 2;
+        BYTE pl_phy_lnk_up : 1;
+        BYTE pl_link_gen2_cap : 1;
+        BYTE pl_link_partner_gen2_supported : 1;
+        BYTE pl_link_upcfg_cap : 1;
+        BYTE pl_sel_lnk_rate : 1;
+        BYTE pl_directed_change_done : 1;
+        BYTE pl_received_hot_rst : 1;
+        BYTE _filler : 7;
+    } rd;
+} DEV_CFG_PHY, *PDEV_CFG_PHY;
+
+typedef struct tdDEVICE_PERFORMANCE {
+    LPSTR SZ_DEVICE_NAME;
+    DWORD PROBE_MAXPAGES;    // 0x400
+    DWORD RX_FLUSH_LIMIT;
+    DWORD MAX_SIZE_RX;        // in data bytes (excl. overhead/TLP headers)
+    DWORD MAX_SIZE_TX;        // in total data (incl. overhead/TLP headers)
+    DWORD DELAY_PROBE_READ;
+    DWORD DELAY_PROBE_WRITE;
+    DWORD DELAY_WRITE;
+    DWORD DELAY_READ;
+    BOOL RETRY_ON_ERROR;
+} DEVICE_PERFORMANCE, *PDEVICE_PERFORMANCE;
+
+#define DEVICE_ID_SP605_FT601                   0
+#define DEVICE_ID_PCIESCREAMER                  1
+#define DEVICE_ID_AC701_FT601                   2
+
+#define PERFORMANCE_PROFILE_SP605_FT601         0
+#define PERFORMANCE_PROFILE_PCIESCREAMER        1
+#define PERFORMANCE_PROFILE_AC701_FT601         2
+#define PERFORMANCE_PROFILE_MAX                 2
+
+const DEVICE_PERFORMANCE PERFORMANCE_PROFILES[PERFORMANCE_PROFILE_MAX + 1] = {
+    {
+        .SZ_DEVICE_NAME = "SP605 / FT601",
+        .PROBE_MAXPAGES = 0x400,
+        .RX_FLUSH_LIMIT = 0x8000,
+        .MAX_SIZE_RX = 0x1f000,
+        .MAX_SIZE_TX = 0x2000,
+        .DELAY_PROBE_READ = 500,
+        .DELAY_PROBE_WRITE = 0,
+        .DELAY_WRITE = 175,
+        .DELAY_READ = 400,
+        .RETRY_ON_ERROR = FALSE
+    }, {
+        // The PCIeScreamer or at least the current bitstream implementation running
+        // on it have a problem with the PCIe link stability which results on lost or
+        // delayed TLPS - workarounds are in place to retry after a delay.
+        .SZ_DEVICE_NAME = "PCIeScreamer",
+        .PROBE_MAXPAGES = 0x400,
+        .RX_FLUSH_LIMIT = 0xfffff000,
+        .MAX_SIZE_RX = 0x1c000,
+        .MAX_SIZE_TX = 0x1000,
+        .DELAY_PROBE_READ = 1000,
+        .DELAY_PROBE_WRITE = 150,
+        .DELAY_WRITE = 0,
+        .DELAY_READ = 500,
+        .RETRY_ON_ERROR = TRUE
+    }, {
+        .SZ_DEVICE_NAME = "AC701 / FT601",
+        .PROBE_MAXPAGES = 0x400,
+        .RX_FLUSH_LIMIT = 0xfffff000,
+        .MAX_SIZE_RX = 0x24000,
+        .MAX_SIZE_TX = 0x8000,
+        .DELAY_PROBE_READ = 500,
+        .DELAY_PROBE_WRITE = 0,
+        .DELAY_WRITE = 0,
+        .DELAY_READ = 200,
+        .RETRY_ON_ERROR = FALSE
+    }
+};
+
+typedef struct tdDEVICE_CONTEXT_FPGA {
+    WORD wDeviceId;
+    WORD wFpgaVersion;
+    WORD wFpgaID;
+    BOOL phySupported;
+    DEV_CFG_PHY phy;
+    DEVICE_PERFORMANCE perf;
+    BOOL isPrintTlp;
+    PTLP_CALLBACK_BUF_MRd pMRdBuffer;
+    struct {
+        PBYTE pb;
+        DWORD cb;
+        DWORD cbMax;
+    } rxbuf;
+    struct {
+        PBYTE pb;
+        DWORD cb;
+        DWORD cbMax;
+    } txbuf;
+    struct {
+        HMODULE hModule;
+        HANDLE hFTDI;
+        ULONG(*pfnFT_Create)(
+            PVOID pvArg, 
+            DWORD dwFlags, 
+            HANDLE *pftHandle
+        );
+        ULONG(*pfnFT_Close)(
+            HANDLE ftHandle
+        );
+        ULONG(*pfnFT_WritePipe)(
+            HANDLE ftHandle,
+            UCHAR ucPipeID,
+            PUCHAR pucBuffer,
+            ULONG ulBufferLength,
+            PULONG pulBytesTransferred,
+            LPOVERLAPPED pOverlapped
+        );
+        ULONG(*pfnFT_ReadPipe)(
+            HANDLE ftHandle,
+            UCHAR ucPipeID,
+            PUCHAR pucBuffer,
+            ULONG ulBufferLength,
+            PULONG pulBytesTransferred,
+            LPOVERLAPPED pOverlapped
+        );
+        ULONG(*pfnFT_AbortPipe)(
+            HANDLE ftHandle,
+            UCHAR ucPipeID
+        );
+    } dev;
+    BOOL(*hRxTlpCallbackFn)(_Inout_ PTLP_CALLBACK_BUF_MRd pBufferMrd, _In_ PBYTE pb, _In_ DWORD cb, _In_opt_ HANDLE hEventCompleted);
+} DEVICE_CONTEXT_FPGA, *PDEVICE_CONTEXT_FPGA;
+
+// STRUCT FROM FTD3XX.h
+typedef struct {
+    USHORT       VendorID;
+    USHORT       ProductID;
+    UCHAR        StringDescriptors[128];
+    UCHAR        Reserved;
+    UCHAR        PowerAttributes;
+    USHORT       PowerConsumption;
+    UCHAR        Reserved2;
+    UCHAR        FIFOClock;
+    UCHAR        FIFOMode;
+    UCHAR        ChannelConfig;
+    USHORT       OptionalFeatureSupport;
+    UCHAR        BatteryChargingGPIOConfig;
+    UCHAR        FlashEEPROMDetection;
+    ULONG        MSIO_Control;
+    ULONG        GPIO_Control;
+} FT_60XCONFIGURATION, *PFT_60XCONFIGURATION;
+
+//-------------------------------------------------------------------------------
+// FPGA implementation below:
+//-------------------------------------------------------------------------------
+
+LPSTR DeviceFPGA_InitializeFTDI(_In_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    LPSTR szErrorReason;
+    CHAR c;
+    DWORD status;
+    ULONG(*pfnFT_GetChipConfiguration)(HANDLE ftHandle, PVOID pvConfiguration);
+    ULONG(*pfnFT_SetChipConfiguration)(HANDLE ftHandle, PVOID pvConfiguration);
+    FT_60XCONFIGURATION oCfgNew, oCfgOld;
+    // Load FTDI Library
+    ctx->dev.hModule = LoadLibrary(L"FTD3XX.dll");
+    if(!ctx->dev.hModule) { 
+        szErrorReason = "Unable to load FTD3XX.dll";
+        goto fail; 
+    }
+    ctx->dev.pfnFT_AbortPipe = (ULONG(*)(HANDLE, UCHAR))
+        GetProcAddress(ctx->dev.hModule, "FT_AbortPipe");
+    ctx->dev.pfnFT_Create = (ULONG(*)(PVOID, DWORD, HANDLE*))
+        GetProcAddress(ctx->dev.hModule, "FT_Create");
+    ctx->dev.pfnFT_Close = (ULONG(*)(HANDLE))
+        GetProcAddress(ctx->dev.hModule, "FT_Close");
+    ctx->dev.pfnFT_ReadPipe = (ULONG(*)(HANDLE, UCHAR, PUCHAR, ULONG, PULONG, LPOVERLAPPED))
+        GetProcAddress(ctx->dev.hModule, "FT_ReadPipe");
+    ctx->dev.pfnFT_WritePipe = (ULONG(*)(HANDLE, UCHAR, PUCHAR, ULONG, PULONG, LPOVERLAPPED))
+        GetProcAddress(ctx->dev.hModule, "FT_WritePipe");
+    pfnFT_GetChipConfiguration = (ULONG(*)(HANDLE, PVOID))GetProcAddress(ctx->dev.hModule, "FT_GetChipConfiguration");
+    pfnFT_SetChipConfiguration = (ULONG(*)(HANDLE, PVOID))GetProcAddress(ctx->dev.hModule, "FT_SetChipConfiguration");
+    if(!ctx->dev.pfnFT_Create) {
+        szErrorReason = "Unable to retrieve required functions from FTD3XX.dll";
+        goto fail; 
+    }
+    // Open FTDI
+    status = ctx->dev.pfnFT_Create(NULL, 0x10 /*FT_OPEN_BY_INDEX*/, &ctx->dev.hFTDI);
+    if(status || !ctx->dev.hFTDI) { 
+        szErrorReason = "Unable to connect to USB/FT601 device";
+        goto fail; 
+    }
+    ctx->dev.pfnFT_AbortPipe(ctx->dev.hFTDI, 0x02);
+    ctx->dev.pfnFT_AbortPipe(ctx->dev.hFTDI, 0x82);
+    // Check FTDI chip configuration and update if required
+    status = pfnFT_GetChipConfiguration(ctx->dev.hFTDI, &oCfgOld);
+    if(status) { 
+        szErrorReason = "Unable to retrieve device configuration";
+        goto fail; 
+    }
+    memcpy(&oCfgNew, &oCfgOld, sizeof(FT_60XCONFIGURATION));
+    oCfgNew.FIFOMode = 0; // FIFO MODE FT245
+    oCfgNew.ChannelConfig = 2; // 1 CHANNEL ONLY
+    oCfgNew.OptionalFeatureSupport = 0;
+    if(memcmp(&oCfgNew, &oCfgOld, sizeof(FT_60XCONFIGURATION))) {
+        printf(
+            "IMPORTANT NOTE! FTDI FT601 USB CONFIGURATION DIFFERS FROM RECOMMENDED\n" \
+            "PLEASE ENSURE THAT ONLY PCILEECH FPGA FTDI FT601 DEVICE IS CONNECED  \n" \
+            "BEFORE UPDATING CONFIGURATION. DO YOU WISH TO CONTINUE Y/N?          \n"
+        );
+        while(TRUE) {
+            c = (CHAR)getchar();
+            if(c == 'Y' || c == 'y') { break; }
+            if(c == 'N' || c == 'n') { 
+                szErrorReason = "User abort required device configuration";
+                goto fail; 
+            }
+            
+        }
+        status = pfnFT_SetChipConfiguration(ctx->dev.hFTDI, &oCfgNew);
+        if(status) { 
+            szErrorReason = "Unable to set required device configuration";
+            goto fail;
+        }
+        printf("FTDI USB CONFIGURATION UPDATED - RESETTING AND CONTINUING ...\n");
+        ctx->dev.pfnFT_Close(ctx->dev.hFTDI);
+        FreeLibrary(ctx->dev.hModule);
+        ctx->dev.hModule = NULL;
+        ctx->dev.hFTDI = NULL;
+        Sleep(3000);
+        return DeviceFPGA_InitializeFTDI(ctx);
+    }
+    return NULL;
+fail:
+    if(ctx->dev.hFTDI && ctx->dev.pfnFT_Close) { ctx->dev.pfnFT_Close(ctx->dev.hFTDI); }
+    if(ctx->dev.hModule) { FreeLibrary(ctx->dev.hModule); }
+    ctx->dev.hModule = NULL;
+    ctx->dev.hFTDI = NULL;
+    return szErrorReason;
+}
+
+VOID DeviceFPGA_ReInitializeFTDI(_In_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    // called to try to recover link in case of instable devices.
+    ctx->dev.pfnFT_Close(ctx->dev.hFTDI);
+    ctx->dev.hFTDI = NULL;
+    Sleep(250);
+    ctx->dev.pfnFT_Create(NULL, 0x10 /*FT_OPEN_BY_INDEX*/, &ctx->dev.hFTDI);
+}
+
+VOID DeviceFPGA_Close(_Inout_ PPCILEECH_CONTEXT ctxPcileech)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    if(!ctx) { return; }
+    if(ctx->dev.hFTDI) { ctx->dev.pfnFT_Close(ctx->dev.hFTDI); }
+    if(ctx->dev.hModule) { FreeLibrary(ctx->dev.hModule); }
+    if(ctx->rxbuf.pb) { LocalFree(ctx->rxbuf.pb); }
+    if(ctx->txbuf.pb) { LocalFree(ctx->txbuf.pb); }
+    LocalFree(ctx);
+    ctxPcileech->hDevice = 0;
+}
+
+BOOL DeviceFPGA_GetSetPHY(_In_ PDEVICE_CONTEXT_FPGA ctx, _In_ BOOL isUpdate)
+{
+    DWORD status;
+    DWORD i, j, cbRxTx, dwStatus;
+    PDWORD pdwData;
+    BYTE pbRx[0x1000];
+    BYTE pbTx[16] = {
+        0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, // dummy: to be overwritten
+        0x00, 0x00, 0x00, 0x00,  0x01, 0x00, 0x03, 0x77, // cmd msg: version (filler)
+    };
+    if(isUpdate) {
+        ctx->phy.magic = 0x77;
+        ctx->phy.tp_cfg = 1;
+        ctx->phy.tp = 4;
+        *(PQWORD)pbTx = _byteswap_uint64(*(PQWORD)&ctx->phy);
+        status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, pbTx, 16, &cbRxTx, NULL);
+        if(status) { return FALSE; }
+        Sleep(10);
+    }
+    *(PQWORD)&ctx->phy = 0;
+    *(PQWORD)pbTx = 0x7731000000000000; // phy read (3) + cfg (1) + magic (77)
+    status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, pbTx, 16, &cbRxTx, NULL);
+    if(status) { return FALSE; }
+    Sleep(10);
+    status = ctx->dev.pfnFT_ReadPipe(ctx->dev.hFTDI, 0x82, pbRx, 0x1000, &cbRxTx, NULL);
+    if(status) { return FALSE; }
+    for(i = 0; i < cbRxTx; i += 32) {
+        while(*(PDWORD)(pbRx + i) == 0x55556666) { // skip over ftdi workaround dummy fillers
+            i += 4;
+            if(i > cbRxTx - 32) { return FALSE; }
+        }
+        dwStatus = *(PDWORD)(pbRx + i);
+        pdwData = (PDWORD)(pbRx + i + 4);
+        if((dwStatus & 0xf0000000) != 0xe0000000) { continue; }
+        for(j = 0; j < 7; j++) {
+            if(((dwStatus & 0x03) == 0x01) && ((*pdwData & 0xffff0000) == 0x77310000)) { // PCIe CFG REPLY
+                // sloppy algorithm below, but it works unless high amount of interfering incoming TLPs
+                *(PQWORD)(&ctx->phy) = _byteswap_uint64(*(PQWORD)(pdwData - 1));
+                return TRUE;
+            }
+            pdwData++;
+            dwStatus >>= 4;
+        }
+    }
+    return FALSE;
+}
+
+BYTE DeviceFPGA_PHY_GetLinkWidth(_In_ PDEVICE_CONTEXT_FPGA ctx) {
+    const BYTE LINK_WIDTH[4] = { 1, 2, 4, 8 };
+    return LINK_WIDTH[ctx->phy.rd.pl_sel_lnk_width];
+}
+
+BYTE DeviceFPGA_PHY_GetPCIeGen(_In_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    return 1 + ctx->phy.rd.pl_sel_lnk_rate;
+}
+
+VOID DeviceFPGA_SetSpeedPCIeGen1(_In_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    if(ctx->phySupported && ctx->phy.rd.pl_sel_lnk_rate) {
+        ctx->phy.wr.pl_directed_link_auton = 1;
+        ctx->phy.wr.pl_directed_link_speed = 0;
+        ctx->phy.wr.pl_directed_link_change = 2;
+        DeviceFPGA_GetSetPHY(ctx, TRUE);
+    }
+}
+
+VOID DeviceFPGA_GetDeviceID_FpgaVersion(_In_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    DWORD status;
+    DWORD cbTX, cbRX, i, j;
+    PBYTE pbRX = LocalAlloc(0, 0x01000000);
+    DWORD dwStatus, dwData, cdwCfg = 0;
+    PDWORD pdwData;
+    BYTE pbTX[24] = {
+        // cfg status: (pcie bus,dev,fn id)
+        0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x01, 0x77,
+        // cmd msg: FPGA bitstream version
+        0x00, 0x00, 0x00, 0x00,  0x01, 0x00, 0x03, 0x77,
+        // cmd msg: FPGA bitstream device id
+        0x00, 0x00, 0x00, 0x00,  0x03, 0x00, 0x03, 0x77
+    };
+    status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, pbTX, 24, &cbTX, NULL);
+    if(status) { goto fail; }
+    Sleep(10);
+    status = ctx->dev.pfnFT_ReadPipe(ctx->dev.hFTDI, 0x82, pbRX, 0x01000000, &cbRX, NULL);
+    if(status) { goto fail; }
+    for(i = 0; i < cbRX; i += 32) {
+        while(*(PDWORD)(pbRX + i) == 0x55556666) { // skip over ftdi workaround dummy fillers
+            i += 4;
+            if(i > cbRX - 32) { goto fail; }
+        }
+        dwStatus = *(PDWORD)(pbRX + i);
+        pdwData = (PDWORD)(pbRX + i + 4);
+        if((dwStatus & 0xf0000000) != 0xe0000000) { continue; }
+        for(j = 0; j < 7; j++) {
+            dwData = *pdwData;
+            if((dwStatus & 0x03) == 0x03) { // CMD REPLY (or filler)
+                if((dwData >> 24) == FPGA_CMD_VERSION) { // FPGA bitstream version
+                    ctx->wFpgaVersion = (WORD)dwData;
+                }
+                if((dwData >> 24) == FPGA_CMD_ID) { // FPGA bitstream device id
+                    ctx->wFpgaID = (WORD)dwData;
+                }
+            }
+            if((dwStatus & 0x03) == 0x01) { // PCIe CFG REPLY
+                if(((++cdwCfg % 2) == 0) && (WORD)dwData) {    // DeviceID: (pcie bus,dev,fn id)
+                    ctx->wDeviceId = (WORD)dwData;
+                }
+            }
+            pdwData++;
+            dwStatus >>= 4;
+        }
+    }
+    ctx->phySupported = (ctx->wFpgaVersion >= 3) ? DeviceFPGA_GetSetPHY(ctx, FALSE) : FALSE;
+fail:
+    LocalFree(pbRX);
+}
+
+VOID DeviceFPGA_SetPerformanceProfile(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _Inout_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    switch(ctx->wFpgaID) {
+        case DEVICE_ID_PCIESCREAMER:
+            memcpy(&ctx->perf, &PERFORMANCE_PROFILES[PERFORMANCE_PROFILE_PCIESCREAMER], sizeof(DEVICE_PERFORMANCE));
+            break;
+        case DEVICE_ID_AC701_FT601:
+            memcpy(&ctx->perf, &PERFORMANCE_PROFILES[PERFORMANCE_PROFILE_AC701_FT601], sizeof(DEVICE_PERFORMANCE));
+            break;
+        default:
+        case DEVICE_ID_SP605_FT601:
+            memcpy(&ctx->perf, &PERFORMANCE_PROFILES[PERFORMANCE_PROFILE_SP605_FT601], sizeof(DEVICE_PERFORMANCE));
+            break;
+    }
+    ctx->perf.DELAY_READ = ctxPcileech->cfg->DeviceOpt[0].isValid ? (DWORD)ctxPcileech->cfg->DeviceOpt[0].qwValue : ctx->perf.DELAY_READ;
+    ctx->perf.DELAY_WRITE = ctxPcileech->cfg->DeviceOpt[1].isValid ? (DWORD)ctxPcileech->cfg->DeviceOpt[1].qwValue : ctx->perf.DELAY_WRITE;
+    ctx->perf.DELAY_PROBE_READ = ctxPcileech->cfg->DeviceOpt[2].isValid ? (DWORD)ctxPcileech->cfg->DeviceOpt[2].qwValue : ctx->perf.DELAY_PROBE_READ;
+}
+
+//-------------------------------------------------------------------------------
+// TLP handling functionality below:
+//-------------------------------------------------------------------------------
+
+BOOL DeviceFPGA_TxTlp(_In_ PDEVICE_CONTEXT_FPGA ctx, _In_ PBYTE pbTlp, _In_ DWORD cbTlp, BOOL fRdKeepalive, BOOL fFlush)
+{
+    DWORD status;
+    PBYTE pbTx;
+    DWORD i, cbTx, cbTxed = 0;
+    if(cbTlp & 0x3) { return FALSE; }
+    if(cbTlp > 2048) { return FALSE; }
+    if(ctx->isPrintTlp) {
+        TLP_Print(pbTlp, cbTlp, TRUE);
+    }
+    // prepare transmit buffer
+    pbTx = ctx->txbuf.pb + ctx->txbuf.cb;
+    cbTx = 2 * cbTlp;
+    for(i = 0; i < cbTlp; i += 4) {
+        *(PDWORD)(pbTx + (i << 1)) = *(PDWORD)(pbTlp + i);
+        *(PDWORD)(pbTx + ((i << 1) + 4)) = 0x77000000;    // TX TLP
+    } 
+    if(cbTlp) {
+        *(PDWORD)(pbTx + ((i << 1) - 4)) = 0x77040000;    // TX TLP VALID LAST
+    }
+    if(fRdKeepalive) {
+        cbTx += 8;
+        *(PDWORD)(pbTx + (i << 1)) = 0xffeeddcc;
+        *(PDWORD)(pbTx + ((i << 1) + 4)) = 0x77020000;    // LOOPBACK TX
+    }
+    ctx->txbuf.cb += cbTx;
+    // transmit
+    if((ctx->txbuf.cb > ctx->perf.MAX_SIZE_TX) || (fFlush && ctx->txbuf.cb)) {
+        status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, ctx->txbuf.pb, ctx->txbuf.cb, &cbTxed, NULL);
+        if(status == 0x20 && ctx->perf.RETRY_ON_ERROR) {
+            DeviceFPGA_ReInitializeFTDI(ctx); // try recovery if possible.
+            status = ctx->dev.pfnFT_WritePipe(ctx->dev.hFTDI, 0x02, ctx->txbuf.pb, ctx->txbuf.cb, &cbTxed, NULL);
+        }
+        ctx->txbuf.cb = 0;
+        return (0 == status);
+    }
+    return TRUE;
+}
+
+#define TLP_RX_MAX_SIZE        2048
+VOID DeviceFPGA_RxTlpSynchronous(_In_ PDEVICE_CONTEXT_FPGA ctx)
+{
+    DWORD status;
+    DWORD i, j, cdwTlp = 0;
+    BYTE pbTlp[TLP_RX_MAX_SIZE];
+    PDWORD pdwTlp = (PDWORD)pbTlp;
+    PDWORD pdwRx = (PDWORD)ctx->rxbuf.pb;
+    DWORD dwStatus, *pdwData;
+    status = ctx->dev.pfnFT_ReadPipe(ctx->dev.hFTDI, 0x82, ctx->rxbuf.pb, ctx->rxbuf.cbMax, &ctx->rxbuf.cb, NULL);
+    if(status == 0x20 && ctx->perf.RETRY_ON_ERROR) {
+        DeviceFPGA_ReInitializeFTDI(ctx); // try recovery if possible.
+        status = ctx->dev.pfnFT_ReadPipe(ctx->dev.hFTDI, 0x82, ctx->rxbuf.pb, ctx->rxbuf.cbMax, &ctx->rxbuf.cb, NULL);
+    }
+    if(status) {
+        ctx->dev.pfnFT_AbortPipe(ctx->dev.hFTDI, 0x82);
+        return;
+    }
+    for(i = 0; i < ctx->rxbuf.cb; i += 32) { // index in 64-bit (QWORD)
+        while(*(PDWORD)(ctx->rxbuf.pb + i) == 0x55556666) { // skip over ftdi workaround dummy fillers
+            i += 4;
+            if(i > ctx->rxbuf.cb - 32) { return; }
+        }
+        dwStatus = *(PDWORD)(ctx->rxbuf.pb + i);
+        pdwData = (PDWORD)(ctx->rxbuf.pb + i + 4);
+        if((dwStatus & 0xf0000000) != 0xe0000000) { 
+            continue; 
+        }
+        for(j = 0; j < 7; j++) {
+            if((dwStatus & 0x03) == 0x00) { // PCIe TLP
+                pdwTlp[cdwTlp] = *pdwData;
+                cdwTlp++;
+                if(cdwTlp >= TLP_RX_MAX_SIZE / sizeof(DWORD)) { return; }
+            }
+            if((dwStatus & 0x07) == 0x04) { // PCIe TLP and LAST
+                if(cdwTlp >= 3) {
+                    if(ctx->isPrintTlp) {
+                        TLP_Print(pbTlp, cdwTlp << 2, FALSE);
+                    }
+                    if(ctx->hRxTlpCallbackFn) {
+                        ctx->hRxTlpCallbackFn(ctx->pMRdBuffer, pbTlp, cdwTlp << 2, NULL);
+                    }
+                } else {
+                    printf("Device Info: SP605 / FT601: Bad PCIe TLP received! Should not happen!\n");
+                }
+                cdwTlp = 0;
+            }
+            pdwData++;
+            dwStatus >>= 4;
+        }
+    }
+}
+
+BOOL DeviceFPGA_ReadDMA_Impl(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwAddr, _Out_ PBYTE pb, _In_ DWORD cb)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    TLP_CALLBACK_BUF_MRd rxbuf;
+    DWORD tx[4], o, i;
+    BOOL is32, isFlush;
+    PTLP_HDR_MRdWr64 hdrRd64 = (PTLP_HDR_MRdWr64)tx;
+    PTLP_HDR_MRdWr32 hdrRd32 = (PTLP_HDR_MRdWr32)tx;
+    if(cb > ctx->perf.MAX_SIZE_RX) { return FALSE; }
+    if(qwAddr % 0x1000) { return FALSE; }
+    if((cb >= 0x1000) && (cb % 0x1000)) { return FALSE; }
+    if((cb < 0x1000) && (cb % 0x8)) { return FALSE; }
+    // prepare
+    rxbuf.cb = 0;
+    rxbuf.pb = pb;
+    rxbuf.cbMax = cb;
+    ctx->pMRdBuffer = &rxbuf;
+    ctx->hRxTlpCallbackFn = TLP_CallbackMRd;
+    // transmit TLPs
+    for(o = 0; o < cb; o += 0x1000) {
+        memset(tx, 0, 16);
+        is32 = qwAddr + o < 0x100000000;
+        if(is32) {
+            hdrRd32->h.TypeFmt = TLP_MRd32;
+            hdrRd32->h.Length = (WORD)((cb < 0x1000) ? cb >> 2 : 0);
+            hdrRd32->RequesterID = ctx->wDeviceId;
+            hdrRd32->Tag = (BYTE)(o >> 12);
+            hdrRd32->FirstBE = 0xf;
+            hdrRd32->LastBE = 0xf;
+            hdrRd32->Address = (DWORD)(qwAddr + o);
+        } else {
+            hdrRd64->h.TypeFmt = TLP_MRd64;
+            hdrRd64->h.Length = (WORD)((cb < 0x1000) ? cb >> 2 : 0);
+            hdrRd64->RequesterID = ctx->wDeviceId;
+            hdrRd64->Tag = (BYTE)(o >> 12);
+            hdrRd64->FirstBE = 0xf;
+            hdrRd64->LastBE = 0xf;
+            hdrRd64->AddressHigh = (DWORD)((qwAddr + o) >> 32);
+            hdrRd64->AddressLow = (DWORD)(qwAddr + o);
+        }
+        for(i = 0; i < 4; i++) {
+            ENDIAN_SWAP_DWORD(tx[i]);
+        }
+        isFlush = ((o % ctx->perf.RX_FLUSH_LIMIT) == (ctx->perf.RX_FLUSH_LIMIT - 0x1000));
+        if(isFlush) {
+            DeviceFPGA_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, TRUE);
+            usleep(ctx->perf.DELAY_WRITE);
+        } else {
+            DeviceFPGA_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, FALSE);
+        }
+    }
+    DeviceFPGA_TxTlp(ctx, NULL, 0, TRUE, TRUE);
+    usleep(ctx->perf.DELAY_READ);
+    DeviceFPGA_RxTlpSynchronous(ctx);
+    ctx->pMRdBuffer = NULL;
+    return rxbuf.cb >= rxbuf.cbMax;
+}
+
+BOOL DeviceFPGA_ReadDMA(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwAddr, _Out_ PBYTE pb, _In_ DWORD cb)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    BOOL result;
+    result = DeviceFPGA_ReadDMA_Impl(ctxPcileech, qwAddr, pb, cb);
+    if(!result && (cb <= 0x1000) && ctx->perf.RETRY_ON_ERROR) {
+        Sleep(100);
+        result = DeviceFPGA_ReadDMA_Impl(ctxPcileech, qwAddr, pb, cb);
+    }
+    return result;
+}
+
+VOID DeviceFPGA_ProbeDMA_Impl(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwAddr, _In_ DWORD cPages, _Inout_ __bcount(cPages) PBYTE pbResultMap)
+{
+    DWORD i, j, cTxTlp = 0;
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    TLP_CALLBACK_BUF_MRd bufMRd;
+    DWORD tx[4];
+    BOOL is32, isFlush;
+    PTLP_HDR_MRdWr64 hdrRd64 = (PTLP_HDR_MRdWr64)tx;
+    PTLP_HDR_MRdWr32 hdrRd32 = (PTLP_HDR_MRdWr32)tx;
+    // split probe into processing chunks if too large...
+    while(cPages > ctx->perf.PROBE_MAXPAGES) {
+        DeviceFPGA_ProbeDMA_Impl(ctxPcileech, qwAddr, ctx->perf.PROBE_MAXPAGES, pbResultMap);
+        cPages -= ctx->perf.PROBE_MAXPAGES;
+        pbResultMap += ctx->perf.PROBE_MAXPAGES;
+        qwAddr += ctx->perf.PROBE_MAXPAGES << 12;
+    }
+    // prepare
+    bufMRd.cb = 0;
+    bufMRd.pb = pbResultMap;
+    bufMRd.cbMax = cPages;
+    ctx->pMRdBuffer = &bufMRd;
+    ctx->hRxTlpCallbackFn = TLP_CallbackMRdProbe;
+    // transmit TLPs
+    for(i = 0; i < cPages; i++) {
+        if(pbResultMap[i]) { continue; } // skip over if page already marked as ok
+        memset(tx, 0, 16);
+        is32 = qwAddr + (i << 12) < 0x100000000;
+        if(is32) {
+            hdrRd32->h.TypeFmt = TLP_MRd32;
+            hdrRd32->h.Length = 1;
+            hdrRd32->RequesterID = ctx->wDeviceId;
+            hdrRd32->FirstBE = 0xf;
+            hdrRd32->LastBE = 0;
+            hdrRd32->Address = (DWORD)(qwAddr + (i << 12) + ((i & 0x1f) << 2)); // 5 low address bits coded into the dword read.
+            hdrRd32->Tag = (BYTE)((i >> 5) & 0x1f); // 5 high address bits coded into tag.
+        } else {
+            hdrRd64->h.TypeFmt = TLP_MRd64;
+            hdrRd64->h.Length = 1;
+            hdrRd64->RequesterID = ctx->wDeviceId;
+            hdrRd64->FirstBE = 0xf;
+            hdrRd64->LastBE = 0;
+            hdrRd64->AddressHigh = (DWORD)((qwAddr + (i << 12)) >> 32);
+            hdrRd64->AddressLow = (DWORD)(qwAddr + (i << 12) + ((i & 0x1f) << 2)); // 5 low address bits coded into the dword read.
+            hdrRd64->Tag = (BYTE)((i >> 5) & 0x1f); // 5 high address bits coded into tag.
+        }
+        for(j = 0; j < 4; j++) {
+            ENDIAN_SWAP_DWORD(tx[j]);
+        }
+        isFlush = (++cTxTlp % 24 == 0);
+        if(isFlush) {
+            DeviceFPGA_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, TRUE);
+            usleep(ctx->perf.DELAY_PROBE_WRITE);
+        } else {
+            DeviceFPGA_TxTlp(ctx, (PBYTE)tx, is32 ? 12 : 16, FALSE, FALSE);
+        }
+    }
+    DeviceFPGA_TxTlp(ctx, NULL, 0, TRUE, TRUE);
+    usleep(ctx->perf.DELAY_PROBE_READ);
+    DeviceFPGA_RxTlpSynchronous(ctx);
+    ctx->hRxTlpCallbackFn = NULL;
+    ctx->pMRdBuffer = NULL;
+}
+
+VOID DeviceFPGA_ProbeDMA(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwAddr, _In_ DWORD cPages, _Inout_ __bcount(cPages) PBYTE pbResultMap)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    DWORD i;
+    DeviceFPGA_ProbeDMA_Impl(ctxPcileech, qwAddr, cPages, pbResultMap);
+    if(ctx->perf.RETRY_ON_ERROR) {
+        for(i = 0; i < cPages; i++) {
+            if(0 == pbResultMap[i]) {
+                Sleep(100);
+                DeviceFPGA_ProbeDMA_Impl(ctxPcileech, qwAddr, cPages, pbResultMap);
+                return;
+            }
+        }
+    }
+}
+
+// write max 128 byte packets.
+BOOL DeviceFPGA_WriteDMA_TXP(_Inout_ PDEVICE_CONTEXT_FPGA ctx, _In_ QWORD qwA, _In_ BYTE bFirstBE, _In_ BYTE bLastBE, _In_ PBYTE pb, _In_ DWORD cb)
+{
+    DWORD txbuf[36], i, cbTlp;
+    PBYTE pbTlp = (PBYTE)txbuf;
+    PTLP_HDR_MRdWr32 hdrWr32 = (PTLP_HDR_MRdWr32)txbuf;
+    PTLP_HDR_MRdWr64 hdrWr64 = (PTLP_HDR_MRdWr64)txbuf;
+    memset(pbTlp, 0, 16);
+    if(qwA < 0x100000000) {
+        hdrWr32->h.TypeFmt = TLP_MWr32;
+        hdrWr32->h.Length = (WORD)(cb + 3) >> 2;
+        hdrWr32->FirstBE = bFirstBE;
+        hdrWr32->LastBE = bLastBE;
+        hdrWr32->RequesterID = ctx->wDeviceId;
+        hdrWr32->Address = (DWORD)qwA;
+        for(i = 0; i < 3; i++) {
+            ENDIAN_SWAP_DWORD(txbuf[i]);
+        }
+        memcpy(pbTlp + 12, pb, cb);
+        cbTlp = (12 + cb + 3) & ~0x3;
+    } else {
+        hdrWr64->h.TypeFmt = TLP_MWr64;
+        hdrWr64->h.Length = (WORD)(cb + 3) >> 2;
+        hdrWr64->FirstBE = bFirstBE;
+        hdrWr64->LastBE = bLastBE;
+        hdrWr64->RequesterID = ctx->wDeviceId;
+        hdrWr64->AddressHigh = (DWORD)(qwA >> 32);
+        hdrWr64->AddressLow = (DWORD)qwA;
+        for(i = 0; i < 4; i++) {
+            ENDIAN_SWAP_DWORD(txbuf[i]);
+        }
+        memcpy(pbTlp + 16, pb, cb);
+        cbTlp = (16 + cb + 3) & ~0x3;
+    }
+    return DeviceFPGA_TxTlp(ctx, pbTlp, cbTlp, FALSE, FALSE);
+}
+
+BOOL DeviceFPGA_WriteDMA(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ QWORD qwA, _In_ PBYTE pb, _In_ DWORD cb)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    BOOL result = TRUE;
+    BYTE be, pbb[4];
+    DWORD cbtx;
+    // TX 1st dword if not aligned
+    if(cb && (qwA & 0x3)) {
+        be = (cb < 3) ? (0xf >> (4 - cb)) : 0xf;
+        be <<= qwA & 0x3;
+        cbtx = min(cb, 4 - (qwA & 0x3));
+        memcpy(pbb + (qwA & 0x3), pb, cbtx);
+        result = DeviceFPGA_WriteDMA_TXP(ctx, qwA & ~0x3, be, 0, pbb, 4);
+        pb += cbtx;
+        cb -= cbtx;
+        qwA += cbtx;
+    }
+    // TX as 128-byte packets (aligned to 128-byte boundaries)
+    while(result && cb) {
+        cbtx = min(128 - (qwA & 0x7f), cb);
+        be = (cbtx & 0x3) ? (0xf >> (4 - (cbtx & 0x3))) : 0xf;
+        result = (cbtx <= 4) ?
+            DeviceFPGA_WriteDMA_TXP(ctx, qwA, be, 0, pb, 4) :
+            DeviceFPGA_WriteDMA_TXP(ctx, qwA, 0xf, be, pb, cbtx);
+        pb += cbtx;
+        cb -= cbtx;
+        qwA += cbtx;
+    }
+    return DeviceFPGA_TxTlp(ctx, NULL, 0, FALSE, TRUE) && result; // Flush and Return.
+}
+
+BOOL DeviceFPGA_ListenTlp(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ DWORD dwTime)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    QWORD tmStart = GetTickCount64();
+    while(GetTickCount64() - tmStart < dwTime) {
+        DeviceFPGA_TxTlp(ctx, NULL, 0, TRUE, TRUE);
+        Sleep(10);
+        DeviceFPGA_RxTlpSynchronous(ctx);
+    }
+    return TRUE;
+}
+
+BOOL DeviceFPGA_WriteTlp(_Inout_ PPCILEECH_CONTEXT ctxPcileech, _In_ PBYTE pbTlp, _In_ DWORD cbTlp)
+{
+    PDEVICE_CONTEXT_FPGA ctx = (PDEVICE_CONTEXT_FPGA)ctxPcileech->hDevice;
+    return DeviceFPGA_TxTlp(ctx, pbTlp, cbTlp, FALSE, TRUE);
+}
+
+BOOL DeviceFPGA_Open(_Inout_ PPCILEECH_CONTEXT ctxPcileech)
+{
+    LPSTR szDeviceError;
+    PDEVICE_CONTEXT_FPGA ctx;
+    ctx = LocalAlloc(LMEM_ZEROINIT, sizeof(DEVICE_CONTEXT_FPGA));
+    if(!ctx) { return FALSE; }
+    ctxPcileech->hDevice = (HANDLE)ctx;
+    szDeviceError = DeviceFPGA_InitializeFTDI(ctx);
+    if(szDeviceError) { goto fail; }
+    DeviceFPGA_GetDeviceID_FpgaVersion(ctx);
+    if(ctxPcileech->cfg->fForcePCIeGen1) { 
+        DeviceFPGA_SetSpeedPCIeGen1(ctx);
+        DeviceFPGA_GetDeviceID_FpgaVersion(ctx);
+    }
+    if(!ctx->wDeviceId) { 
+        szDeviceError = "Unable to retrieve required Device PCIe ID";
+        goto fail;
+    }
+    DeviceFPGA_SetPerformanceProfile(ctxPcileech, ctx);
+    ctx->rxbuf.cbMax = (DWORD)(1.30 * ctx->perf.MAX_SIZE_RX + 0x1000);  // buffer size tuned to lowest possible (+margin) for performance.
+    ctx->rxbuf.pb = LocalAlloc(0, ctx->rxbuf.cbMax);
+    if(!ctx->rxbuf.pb) { goto fail; }
+    ctx->txbuf.cbMax = ctx->perf.MAX_SIZE_TX + 0x10000;
+    ctx->txbuf.pb = LocalAlloc(0, ctx->txbuf.cbMax);
+    if(!ctx->txbuf.pb) { goto fail; }
+    ctx->isPrintTlp = ctxPcileech->cfg->fVerboseExtra;
+    // set callback functions and fix up config
+    ctxPcileech->cfg->dev.tp = PCILEECH_DEVICE_FPGA;
+    ctxPcileech->cfg->dev.qwMaxSizeDmaIo = ctx->perf.MAX_SIZE_RX;
+    ctxPcileech->cfg->dev.qwAddrMaxNative = 0x0000ffffffffffff;
+    ctxPcileech->cfg->dev.fPartialPageReadSupported = TRUE;
+    ctxPcileech->cfg->dev.pfnClose = DeviceFPGA_Close;
+    ctxPcileech->cfg->dev.pfnProbeDMA = ctx->perf.PROBE_MAXPAGES ? DeviceFPGA_ProbeDMA : NULL;
+    ctxPcileech->cfg->dev.pfnReadDMA = DeviceFPGA_ReadDMA;
+    ctxPcileech->cfg->dev.pfnWriteDMA = DeviceFPGA_WriteDMA;
+    ctxPcileech->cfg->dev.pfnWriteTlp = DeviceFPGA_WriteTlp;
+    ctxPcileech->cfg->dev.pfnListenTlp = DeviceFPGA_ListenTlp;
+    // return
+    if(ctxPcileech->cfg->fVerbose) { 
+        printf("FPGA: Device Info: %s PCIe gen%i x%i [%i,%i,%i]\n", ctx->perf.SZ_DEVICE_NAME, DeviceFPGA_PHY_GetPCIeGen(ctx), DeviceFPGA_PHY_GetLinkWidth(ctx), ctx->perf.DELAY_READ, ctx->perf.DELAY_WRITE, ctx->perf.DELAY_PROBE_READ);
+    }
+    return TRUE;
+fail:
+    if(szDeviceError && (ctxPcileech->cfg->fVerbose || (ctxPcileech->cfg->dev.tp == PCILEECH_DEVICE_FPGA))) {
+        printf("FPGA: ERROR: %s.\n", szDeviceError);
+    }
+    DeviceFPGA_Close(ctxPcileech);
+    return FALSE;
+}
+
+#endif /* WIN32 */
+#if defined(LINUX) || defined(ANDROID)
+
+#include "devicefpga.h"
+
+BOOL DeviceFPGA_Open(_Inout_ PPCILEECH_CONTEXT ctx)
+{
+    if(ctx->cfg->dev.tp == PCILEECH_DEVICE_FPGA) {
+        printf("FPGA: Failed. FPGA device currently only supported in PCILeech for Windows.");
+    }
+    return FALSE;
+}
+
+#endif /* LINUX || ANDROID */
diff --git a/pcileech/devicefpga.h b/pcileech/devicefpga.h
new file mode 100644
index 0000000..0d9a05a
--- /dev/null
+++ b/pcileech/devicefpga.h
@@ -0,0 +1,20 @@
+// devicefpga.h : definitions related to the:
+//     - Xilinx SP605 dev board flashed with PCILeech bitstream and FTDI UMFT601X-B addon-board.
+//     - Xilinx AC701 dev board flashed with PCILeech bitstream and FTDI UMFT601X-B addon-board.
+//     - PCIeScreamer board flashed with PCILeech bitstream.
+//
+// (c) Ulf Frisk, 2017-2018
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+#ifndef __DEVICEFPGA_H__
+#define __DEVICEFPGA_H__
+#include "pcileech.h"
+
+/*
+* Open a connection to the PCILeech flashed FPGA device.
+* -- ctx
+* -- result
+*/
+BOOL DeviceFPGA_Open(_Inout_ PPCILEECH_CONTEXT ctx);
+
+#endif /* __DEVICEFPGA_H__ */
diff --git a/pcileech/help.c b/pcileech/help.c
index b71446e..8ef57d0 100644
--- a/pcileech/help.c
+++ b/pcileech/help.c
@@ -34,7 +34,8 @@ VOID Help_ShowGeneral()
 		" loaded on program exit ( except for the kmdload command ).                    \n" \
 		" KMD mode may access all memory (available to the kernel of the target system).\n" \
 		" DMA mode may only access lower 4GB of memory if USB3380 hardware is used.     \n" \
-		" DMA mode may access all memory if FPGA based hardware such as SP605 is used.  \n" \
+		" DMA mode may access all memory if FPGA based hardware is used such as the:    \n" \
+		" SP605, AC701 and PCIeScreamer.                                                \n" \
 		" For detailed help about a specific command type:  pcileech.exe <command> -help\n" \
 		" General syntax: pcileech.exe <command> [-<optionname1> <optionvalue1>] ...    \n" \
 		" Valid commands and valid MODEs     [ and options ]                            \n" \
@@ -63,11 +64,10 @@ VOID Help_ShowGeneral()
 		"   mac_fvrecover2         DMA                                                  \n" \
 		"   mac_disablevtd         DMA                                                  \n" \
 		" Valid options:                                                                \n" \
-		"   -min : memory min address, valid range: 0x0..0xffffffffffffffff             \n" \
+		"   -min : memory min address, valid range: 0x0 .. 0xffffffffffffffff           \n" \
 		"          default: 0x0                                                         \n" \
-		"   -max : memory max address, valid range: 0x0..0xffffffffffffffff             \n" \
-		"          default: <max supported by device> (0xffffffff/4GB for USB3380)      \n" \
-		"          default: actual memory size in KMD mode.                             \n" \
+		"   -max : memory max address, valid range: 0x0 .. 0xffffffffffffffff           \n" \
+		"          default: <max supported by device> (FPGA = no limit, USB3380 = 4GB)  \n" \
 		"   -out : name of output file.                                                 \n" \
 		"          default: pcileech-<minaddr>-<maxaddr>-<date>-<time>.raw              \n" \
 		"          No output file will be created if parameter is set to none or null.  \n" \
@@ -76,27 +76,25 @@ VOID Help_ShowGeneral()
 		"   -vv  : extra verbose option. Same as -v but even more detailed output.      \n" \
 		"          Option shows raw PCIe TLPs received/sent if FPGA is used.            \n" \
 		"   -v   : verbose option. Additional information is displayed in the output.   \n" \
-		"          The memory map is shown when searching/dumping memory as an example. \n" \
-		"          Affects all modes and commands.                                      \n" \
-		"          Option has no value. Example: -v                                     \n" \
+		"          Affects all modes and commands. Option has no value. Example: -v     \n" \
 		"   -force: force reads and writes even though target memory is marked as not   \n" \
 		"          accessible. Dangerous! Affects all modes and commands.               \n" \
 		"          Option has no value. Example: -force                                 \n" \
 		"   -usb2: force USB2 mode (only for USB3380 device). USB2 will reduce transfer \n" \
-		"          speed but may increase stability.                                    \n" \
-		"          Affects all modes and commands.                                      \n" \
-		"          Option has no value. Example: -usb2                                  \n" \
+		"          speed but increase stability. Option has no value. Example: -usb2    \n" \
+		"   -pcie_gen1: force PCIe Gen1 mode. For FPGA devices capable of PCIe Gen2.    \n" \
+		"          May increase stability. Option has no value. Example: -pcie_gen1     \n" \
 		"   -iosize: max DMA i/o size. Hardware DMA requests larger than iosize will    \n" \
 		"          be discarded. Affects all modes and commands.                        \n" \
 		"   -tlpwait: Wait in seconds while listening for PCIe TLPs.                    \n" \
 		"          Wait occurs after any other actions have been completed.             \n" \
 		"   -device: force the use of a specific hardware device instead of auto-detect.\n" \
 		"          Affects all modes and commands.                                      \n" \
-		"          Valid options: USB3380, SP605_FT601, SP605_TCP                       \n" \
+		"          Valid options: USB3380, FPGA, SP605_TCP                              \n" \
 		"   -device-addr: Remote address for -device SP605_TCP.                         \n" \
 		"   -device-port: Remote TCP port for -device SP605_TCP. Default value: 28472.  \n" \
 		"   -device-opt[0-3]: Optional additional device configuration for some devices.\n" \
-		"          SP605_FT605 device: NB! 0 = default!. -device-opt0 = delay read uS   \n" \
+		"          FPGA device (NB! 0 = default!): -device-opt0 = delay read uS         \n" \
 		"                -device-opt1 = delay write uS, -device-opt2 = delay probe uS   \n" \
 		"   -help: show help about the selected command or implant and then exit        \n" \
 		"          without running the command. Affects all modes and commands.         \n" \
@@ -109,12 +107,10 @@ VOID Help_ShowGeneral()
 		"          default: 0                                                           \n" \
 		"   -pt  : trigger KMD insertion by automatic page table hijack.                \n" \
 		"          Option has no value. Example: -pt                                    \n" \
-		"          Only used in conjunction with -kmd option to trigger KMD insertion   \n" \
-		"          by page table hijack. Only recommended to use with care on computers \n" \
-		"          with 4GB+ RAM when kernel is located in high-memory (Windows 10).    \n" \
-		"          Insertion may trigger system crash unless signature exactly matches. \n" \
+		"          Used in conjunction with -kmd option to trigger KMD insertion by page\n" \
+		"          table hijack. Only recommended to use with care on computers with    \n" \
+		"          4GB+ RAM when kernel is located in high-memory (Windows 10).         \n" \
 		"   -cr3 : base address of system page table / CR3 CPU register.                \n" \
-		"          Insertion may trigger system crash unless signature exactly matches. \n" \
 		"   -efibase : base address of EFI_SYSTEM_TABLE (IBI SYST) used when inserting  \n" \
 		"          UEFI 'kernel' modules.                                               \n" \
 		"   -kmd : address of already loaded kernel module helper (KMD).                \n" \
@@ -143,21 +139,20 @@ VOID Help_ShowInfo()
 {
 	printf(
 		" PCILEECH INFORMATION                                                          \n" \
-		" PCILeech (c) 2016, 2017 Ulf Frisk                                             \n" \
-		" Version: 2.5.1                                                                \n" \
+		" PCILeech (c) 2016-2018 Ulf Frisk                                              \n" \
+		" Version: 2.6                                                                  \n" \
 		" License: GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007                 \n" \
 		" Contact information: pcileech@frizk.net                                       \n" \
 		" System requirements: 64-bit Windows 7, 10 or Linux.                           \n" \
 		" Other project references:                                                     \n" \
 		"   PCILeech          - https://github.com/ufrisk/pcileech                      \n" \
-		"   Slotscreamer      - https://github.com/NSAPlayset/SLOTSCREAMER              \n" \
-		"   Inception         - https://github.com/carmaa/inception                     \n" \
-		"   Google USB driver - https://developer.android.com/sdk/win-usb.html#download \n" \
-		"   FTDI FT601:       - http://www.ftdichip.com/Drivers/D3XX.htm                \n" \
+		"   PCILeech-FPGA     - https://github.com/ufrisk/pcileech-fpga                 \n" \
+		"   Google USB Driver - https://developer.android.com/sdk/win-usb.html          \n" \
+		"   FTDI FT601 Driver - http://www.ftdichip.com/Drivers/D3XX.htm                \n" \
 		"   Dokany            - https://github.com/dokan-dev/dokany/releases/latest     \n" \
 		" ----------------                                                              \n" \
 		" Use with USB3380 hardware programmed as a PCILeech device.                    \n" \
-		" Use with SP605/FT601 harware programmed as a PCILeech FPGA device.            \n" \
+		" Use with FPGA harware programmed as a PCILeech FPGA device.                   \n" \
 		" Use with SP605 hardware / 'PCI Express DIY hacking toolkit' by cr4sh/@d_olex. \n\n" \
 		" ----------------                                                              \n" \
 		" Driver information (USB3380/Windows):                                         \n" \
@@ -165,12 +160,11 @@ VOID Help_ShowInfo()
 		"   device masks as a Google Glass. Please download and install the Google USB  \n" \
 		"   driver before proceeding by using the USB3380 device. USB3 is recommended   \n" \
 		"   to performance reasons (USB2 will work but impact performance).             \n" \
-		" Driver information (SP605/FT601/Windows):                                     \n" \
-		"   The PCILeech programmed SP605 FPGA development board with the FT601 USB3    \n" \
-		"   addon board requires drivers for Windows. The drivers are on Windows update \n" \
-		"   and is installed automatically at first use. PCILeech also requires the FTDI\n" \
-		"   application library (DLL). Download this library from the FTDI web site and \n" \
-		"   place the 64-bit FTD3XX.dll alongside pcileech.exe.                         \n" \
+		" Driver information (FPGA/FT601/Windows):                                      \n" \
+		"   The PCILeech programmed FPGA board with FT601 USB3 requires drivers for USB.\n" \
+		"   The drivers are on Windows update and is installed at first use.            \n" \
+		"   PCILeech also requires the FTDI application library (DLL). Download DLL from\n" \
+		"   FTDI web site and place the 64-bit FTD3XX.dll alongside pcileech.exe.       \n" \
 		" Driver information (Dokany/Windows):                                          \n" \
 		"   To be able to use the 'mount' functionality for filesystem browsing and live\n" \
 		"   memory file access PCILeech requires Dokany to be installed for virtual file\n" \
@@ -336,11 +330,26 @@ VOID Help_ShowDetailed(_In_ PCONFIG pCfg)
 			" 2) mount file system and live RAM of target as X: drive letter.               \n" \
 			"    pcileech mount -kmd 0x7fffe000 -s X                                        \n");
 		break;
+	case DISPLAY:
+		printf(
+			" DISPLAY MEMORY ON SCREEN.                                                     \n" \
+			" MODES   : DMA, KMD                                                            \n" \
+			" OPTIONS : -min, -max (optional)                                               \n" \
+			" The memory contents between min and max is shown on screen.                   \n" \
+			" Use the -min option to specify the memory location.                           \n" \
+			" EXAMPLES:      (example kernel module is loaded at address 0x7fffe000)        \n" \
+			" 1) display memory starting at physical address 0x1000.                        \n" \
+			"    pcileech display -min 0x1000                                               \n" \
+			" 2) display memory between 0x1000 and 0x2fff.                                  \n" \
+			"    pcileech display -min 0x1000 -max 0x2fff                                   \n" \
+			" 3) display memory starting at physical address 0x140000000 (5GB).             \n" \
+			"    pcileech display -min 0x140000000 -kmd 0x7fffe000                          \n");
+		break;
 	case PAGEDISPLAY:
 		printf(
 			" DISPLAY A MEMORY PAGE ON SCREEN.                                              \n" \
 			" MODES   : DMA, KMD                                                            \n" \
-			" OPTIONS : -min, -force                                                        \n" \
+			" OPTIONS : -min                                                                \n" \
 			" The memory contents of a single page (4096 bytes) is shown on screen. Use the \n" \
 			" -min option to specify the memory location. If the -min option is not aligned \n" \
 			" the specified memory address will be truncated. It is also possible to force  \n" \
diff --git a/pcileech/memdump.c b/pcileech/memdump.c
index 7809c10..f91fb72 100644
--- a/pcileech/memdump.c
+++ b/pcileech/memdump.c
@@ -140,6 +140,7 @@ VOID ActionMemoryProbe(_Inout_ PPCILEECH_CONTEXT ctx)
 	PageStatInitialize(&ps, ctx->cfg->qwAddrMin, ctx->cfg->qwAddrMax, "Probing Memory", FALSE, TRUE);
 	while(qwA < ctx->cfg->qwAddrMax) {
 		cPages = min(MEMORY_PROBE_PAGES_PER_SWEEP, (ctx->cfg->qwAddrMax - qwA) / 0x1000);
+        memset(pbResultMap, 0, cPages);
 		if(!DeviceProbeDMA(ctx, qwA, (DWORD)cPages, pbResultMap)) {
 			PageStatClose(&ps);
 			printf("Memory Probe: Failed. Unsupported hardware (USB3380) or other failure.\n");
diff --git a/pcileech/oscompatibility.c b/pcileech/oscompatibility.c
index 7497ea5..965ab0a 100644
--- a/pcileech/oscompatibility.c
+++ b/pcileech/oscompatibility.c
@@ -10,6 +10,7 @@
 VOID usleep(_In_ DWORD us)
 {
 	QWORD tmFreq, tmStart, tmNow, tmThreshold;
+	if(us == 0) { return; }
 	QueryPerformanceFrequency((PLARGE_INTEGER)&tmFreq);
 	tmThreshold = tmFreq * us / (1000 * 1000);	// dw_uS uS
 	QueryPerformanceCounter((PLARGE_INTEGER)&tmStart);
diff --git a/pcileech/pcileech.c b/pcileech/pcileech.c
index 772da8a..b0a26ec 100644
--- a/pcileech/pcileech.c
+++ b/pcileech/pcileech.c
@@ -91,6 +91,10 @@ BOOL PCILeechConfigIntialize(_In_ DWORD argc, _In_ char* argv[], _Inout_ PPCILEE
 			ctx->cfg->fForceUsb2 = TRUE;
 			i++;
 			continue;
+		} else if((0 == _stricmp(argv[i], "-pcie_gen1")) || (0 == _stricmp(argv[i], "-pcie-gen1"))) {
+			ctx->cfg->fForcePCIeGen1 = TRUE;
+			i++;
+			continue;
 		} else if(0 == _stricmp(argv[i], "-v")) {
 			ctx->cfg->fVerbose = TRUE;
 			i++;
@@ -119,8 +123,8 @@ BOOL PCILeechConfigIntialize(_In_ DWORD argc, _In_ char* argv[], _Inout_ PPCILEE
 			ctx->cfg->dev.tp = PCILEECH_DEVICE_NA;
 			if(0 == _stricmp(argv[i + 1], "usb3380")) { 
 				ctx->cfg->dev.tp = PCILEECH_DEVICE_USB3380;
-			} else if(0 == _stricmp(argv[i + 1], "sp605_ft601")) {
-				ctx->cfg->dev.tp = PCILEECH_DEVICE_SP605_FT601;
+			} else if(0 == _stricmp(argv[i + 1], "fpga")) {
+				ctx->cfg->dev.tp = PCILEECH_DEVICE_FPGA;
 			} else if(0 == _stricmp(argv[i + 1], "sp605_tcp")) {
 				ctx->cfg->dev.tp = PCILEECH_DEVICE_SP605_TCP;
 			}
@@ -153,7 +157,8 @@ BOOL PCILeechConfigIntialize(_In_ DWORD argc, _In_ char* argv[], _Inout_ PPCILEE
 		} else if(2 == strlen(argv[i]) && '0' <= argv[i][1] && '9' >= argv[i][1]) { // -0..9 param
 			ctx->cfg->qwDataIn[argv[i][1] - '0'] = Util_GetNumeric(argv[i + 1]);
 		} else if(!memcmp(argv[i], "-device-opt", 11) && (argv[i][11] >= '0') && (argv[i][11] <= '3')) { // -devopt[0-3] (device options)
-			ctx->cfg->qwDeviceOpt[argv[i][11] - '0'] = Util_GetNumeric(argv[i + 1]);
+			ctx->cfg->DeviceOpt[argv[i][11] - '0'].qwValue = Util_GetNumeric(argv[i + 1]);
+			ctx->cfg->DeviceOpt[argv[i][11] - '0'].isValid = TRUE;
 		}
 		i += 2;
 	}
@@ -211,15 +216,7 @@ int main(_In_ int argc, _In_ char* argv[])
 		printf("PCILEECH: Out of memory.\n");
 		return 1;
 	}
-	//LPSTR szTMP[] = { "", "-device", "SP605_TCP", "-device-addr", "192.168.1.2", "dump", "-out", "none", "-min", "0x100000000", "-max", "0x110010000" };
-	//LPSTR szTMP[] = { "", "kmdload", "-kmd", "win10x64_ntfs_20170919_14240.kmd", "-min", "0x100000000" };
-	//LPSTR szTMP[] = { "", "mount", "-kmd", "win10_x64"};
-	//LPSTR szTMP[] = { "", "write", "-min", "0xc6010000", "-in", "c:\\temp\\16M_zero.raw"};
-	//LPSTR szTMP[] = { "", "pagedisplay", "-min", "0x1000", "-vv"};
-	///LPSTR szTMP[] = { "", "dump", "-out", "none", "-min", "0x100000000", "-max", "0x120000000"};
-	//LPSTR szTMP[] = { "", "tlp", "-in", "00000000c30000ffc1000000", "-vv"};
-	//result = PCILeechConfigIntialize(sizeof(szTMP) / sizeof(LPSTR), szTMP, ctx);
-	result = PCILeechConfigIntialize((DWORD)argc, argv, ctx);
+    result = PCILeechConfigIntialize((DWORD)argc, argv, ctx);
 	if(!result) {
 		Help_ShowGeneral();
 		PCILeechFreeContext(ctx);
diff --git a/pcileech/pcileech.h b/pcileech/pcileech.h
index 14d0dae..879f734 100644
--- a/pcileech/pcileech.h
+++ b/pcileech/pcileech.h
@@ -48,7 +48,7 @@ typedef enum tdActionType {
 typedef enum tdPCILEECH_DEVICE_TYPE {
 	PCILEECH_DEVICE_NA,
 	PCILEECH_DEVICE_USB3380,
-	PCILEECH_DEVICE_SP605_FT601,
+	PCILEECH_DEVICE_FPGA,
 	PCILEECH_DEVICE_SP605_TCP
 } PCILEECH_DEVICE_TYPE;
 
@@ -59,12 +59,17 @@ typedef struct tdDeviceConfig {
 	BOOL fPartialPageReadSupported;
 	BOOL(*pfnReadDMA)(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _Out_ PBYTE pb, _In_ DWORD cb);
 	BOOL(*pfnWriteDMA)(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ PBYTE pb, _In_ DWORD cb);
-	VOID(*pfnProbeDMA)(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ DWORD cPages, _Out_ __bcount(cPages) PBYTE pbResultMap);
+	VOID(*pfnProbeDMA)(_Inout_ PPCILEECH_CONTEXT ctx, _In_ QWORD qwAddr, _In_ DWORD cPages, _Inout_ __bcount(cPages) PBYTE pbResultMap);
 	BOOL(*pfnWriteTlp)(_Inout_ PPCILEECH_CONTEXT ctx, _In_ PBYTE pb, _In_ DWORD cb);
 	BOOL(*pfnListenTlp)(_Inout_ PPCILEECH_CONTEXT ctx, _In_ DWORD dwTime);
 	VOID(*pfnClose)(_Inout_ PPCILEECH_CONTEXT ctx);
 } DEVICE_CONFIG;
 
+typedef struct tdCONFIG_OPTION {
+	QWORD isValid;
+	QWORD qwValue;
+} CONFIG_OPTION;
+
 typedef struct tdConfig {
 	QWORD qwAddrMin;
 	QWORD qwAddrMax;
@@ -76,7 +81,7 @@ typedef struct tdConfig {
 	QWORD cbIn;
 	CHAR szInS[MAX_PATH];
 	QWORD qwDataIn[10];
-	QWORD qwDeviceOpt[4];
+	CONFIG_OPTION DeviceOpt[4];
 	ACTION_TYPE tpAction;
 	CHAR szSignatureName[MAX_PATH];
 	CHAR szKMDName[MAX_PATH];
@@ -91,7 +96,8 @@ typedef struct tdConfig {
 	BOOL fForceRW;
 	BOOL fShowHelp;
 	BOOL fOutFile;
-	BOOL fForceUsb2;	// USB3380
+	BOOL fForceUsb2;		// USB3380
+	BOOL fForcePCIeGen1;	// FPGA
 	BOOL fVerbose;
 	BOOL fVerboseExtra;
 	BOOL fDebug;
diff --git a/pcileech/pcileech.vcxproj b/pcileech/pcileech.vcxproj
index a64e37f..17efa9f 100644
--- a/pcileech/pcileech.vcxproj
+++ b/pcileech/pcileech.vcxproj
@@ -85,8 +85,8 @@
   <ItemGroup>
     <ClInclude Include="device.h" />
     <ClInclude Include="device3380.h" />
-    <ClInclude Include="device605_601.h" />
     <ClInclude Include="device605_tcp.h" />
+    <ClInclude Include="devicefpga.h" />
     <ClInclude Include="dokan.h" />
     <ClInclude Include="executor.h" />
     <ClInclude Include="extra.h" />
@@ -105,8 +105,8 @@
   <ItemGroup>
     <ClCompile Include="device.c" />
     <ClCompile Include="device3380.c" />
-    <ClCompile Include="device605_601.c" />
     <ClCompile Include="device605_tcp.c" />
+    <ClCompile Include="devicefpga.c" />
     <ClCompile Include="executor.c" />
     <ClCompile Include="extra.c" />
     <ClCompile Include="help.c" />
diff --git a/pcileech/pcileech.vcxproj.filters b/pcileech/pcileech.vcxproj.filters
index 17d6a0a..fb262a1 100644
--- a/pcileech/pcileech.vcxproj.filters
+++ b/pcileech/pcileech.vcxproj.filters
@@ -66,10 +66,10 @@
     <ClInclude Include="oscompatibility.h">
       <Filter>Header Files</Filter>
     </ClInclude>
-    <ClInclude Include="device605_601.h">
+    <ClInclude Include="device605_tcp.h">
       <Filter>Header Files</Filter>
     </ClInclude>
-    <ClInclude Include="device605_tcp.h">
+    <ClInclude Include="devicefpga.h">
       <Filter>Header Files</Filter>
     </ClInclude>
   </ItemGroup>
@@ -116,10 +116,10 @@
     <ClCompile Include="oscompatibility.c">
       <Filter>Source Files</Filter>
     </ClCompile>
-    <ClCompile Include="device605_601.c">
+    <ClCompile Include="device605_tcp.c">
       <Filter>Source Files</Filter>
     </ClCompile>
-    <ClCompile Include="device605_tcp.c">
+    <ClCompile Include="devicefpga.c">
       <Filter>Source Files</Filter>
     </ClCompile>
   </ItemGroup>
diff --git a/pcileech_files/pcileech b/pcileech_files/pcileech
index a97a219..f2c9c59 100644
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diff --git a/readme.md b/readme.md
index d185bad..86b2842 100644
--- a/readme.md
+++ b/readme.md
@@ -6,7 +6,7 @@ PCILeech supports multiple hardware. USB3380 based hardware is only able to read
 
 PCILeech is capable of inserting a wide range of kernel implants into the targeted kernels - allowing for easy access to live ram and the file system via a "mounted drive". It is also possible to remove the logon password requirement, loading unsigned drivers, executing code and spawn system shells. PCIleech runs on Windows/Linux/Android. Supported target systems are currently the x64 versions of: UEFI, Linux, FreeBSD, macOS and Windows.
 
-<img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_mbp.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_m2.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_shadow.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_dump.gif" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_mount.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/314e527e13e78edd44cc6db2b7c05cfa4a1ce322/_gh_android.jpg" height="150"/>
+<img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_mbp.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_m2.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_shadow.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/314e527e13e78edd44cc6db2b7c05cfa4a1ce322/_gh_android.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_dump.gif" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/ab5032dac2600acf1480d81ac265b66fecaaa9b2/_gh_ac701_pcileech_main.jpg" height="150"/><img src="https://gist.github.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/ab5032dac2600acf1480d81ac265b66fecaaa9b2/_gh_pciescreamer_pcileech_main.jpg" height="150"/>
 
 Capabilities:
 =============
@@ -30,49 +30,20 @@ Capabilities:
 
 \*) macOS High Sierra is not supported.
 
-Installing PCILeech:
-====================
-Please ensure you do have the most recent version of PCILeech by visiting the PCILeech github repository at: https://github.com/ufrisk/pcileech
-
-Clone the PCILeech Github repository. The binaries are found in pcileech_files and should work on 64-bit Windows and Linux. Please copy all files from pcileech_files since some files contains additional modules and signatures.
-
-#### Windows:
-The Google Android USB driver also have to be installed if USB3380 hardware is used. Download the Google Android USB driver from: http://developer.android.com/sdk/win-usb.html#download Unzip the driver. Open Device Manager. Right click on the computer, choose add legacy hardware. Select install the hardware manually. Click Have Disk. Navigate to the Android Driver, select android_winusb.inf and install.
-
-FTDI drivers have to be installed if FPGA is used with FT601 USB3 addon card. FTDI drivers will installed automatically on Windows from Windows Update at first connection. PCILeech also requires 64-bit [`FTD3XX.dll`](http://www.ftdichip.com/Drivers/D3XX/FTD3XXLibrary_v1.2.0.6.zip) which must be downloaded from FTDI and placed alongside `pcileech.exe`.
-
-To mount live ram and target file system as drive in Windows the Dokany file system library must be installed. Please download and install the latest version of Dokany at: https://github.com/dokan-dev/dokany/releases/latest
-
-#### Linux:
-PCILeech on Linux must be run as root. PCILeech also requires libusb. Libusb is probably installed by default - if not install it by running: `apt-get install libusb-1.0-0`.
-
-#### Android:
-Separate instructions for [Android](Android.md).
-
 Hardware:
 =================
-PCILeech supports multiple hardware devices. Please check out the [PCILeech FPGA project](https://github.com/ufrisk/pcileech-fpga/) for information about supported FPGA based hardware. Please find a device comparision table below. More information about USB3380 devices are also found below.
+PCILeech supports multiple hardware devices. Please check out the [PCILeech FPGA project](https://github.com/ufrisk/pcileech-fpga/) for information about supported FPGA based hardware. Please check out [PCILeech USB3380](usb3380.md) for information about USB3380 based hardware. 
 
-| Device      | Type    | Interface | Speed   | 64-bit memory access | PCIe TLP access |
-| ----------- | ------- | --------- | ------- | -------------------- | --------------- |
-| USB3380-EVB | USB3380 | USB3      | 150MB/s | No (via KMD only)    | No              |
-| PP3380      | USB3380 | USB3      | 150MB/s | No (via KMD only)    | No              |
-| SP605/FT601 | FPGA    | USB3      |  75MB/s | Yes                  | Yes             |
-| SP605/TCP   | FPGA    | TCP/IP    | 100kB/s | Yes                  | Yes             |
+Please find a device comparision table below.
 
-Hardware (USB3380):
-=================
-PCILeech use the PLX Technologies USB3380 chip. The actual chip can be purchased for around $15, but it's more convenient to purchase a development board on which the chip is already mounted. Development boards can be purchased from BPlus Technology, or on eBay / Ali Express. Please note that adapters may be required too depending on your requirements. In addition to the USB3380 PCILeech also supports not yet released FPGA based hardware.
-
-http://www.bplus.com.tw/PLX.html
-
-The hardware confirmed working is:
-* USB3380-EVB mini-PCIe card.
-* PP3380-AB PCIe card.
-
-Please note that the ExpressCard EC3380-AB is not working!
-
-Please note that the USB3380-AB EVK-RC kit is not working!
+| Device                                    | Type | Interface | Speed | 64-bit memory access | PCIe TLP access |
+| -------------------------------------------------------- | ------- | ---- | ------- | ----------------- | --- |
+| [AC701/FT601](https://github.com/ufrisk/pcileech-fpga/)  | FPGA    | USB3 | 150MB/s | Yes               | Yes |
+| [PCIeScreamer](https://github.com/ufrisk/pcileech-fpga/) | FPGA    | USB3 | 100MB/s | Yes               | Yes |
+| [SP605/FT601](https://github.com/ufrisk/pcileech-fpga/)  | FPGA    | USB3 |  75MB/s | Yes               | Yes |
+| [SP605/TCP](https://github.com/ufrisk/pcileech-fpga/)    | FPGA  | TCP/IP | 100kB/s | Yes               | Yes |
+| [USB3380-EVB](usb3380.md)                                | USB3380 | USB3 | 150MB/s | No (via KMD only) | No  |
+| [PP3380](usb3380.md)                                     | USB3380 | USB3 | 150MB/s | No (via KMD only) | No  |
 
 Recommended adapters:
 * PE3B - ExpressCard to mini-PCIe.
@@ -84,15 +55,24 @@ Recommended adapters:
 
 Please note that other adapters may also work.
 
-Flashing Hardware (USB3380):
-==================
-In order to turn the USB3380 development board into a PCILeech device it must be flashed. Flashing may be done in Windows 10 (as administrator) or in Linux (as root). The board must be connected to the system via PCIe when performing the initial flash.
+Installing PCILeech:
+====================
+Please ensure you do have the most recent version of PCILeech by visiting the PCILeech github repository at: https://github.com/ufrisk/pcileech
 
-To flash in Windows 10 unzip all contents of the ` flash.zip ` archive found in ` pcileech_files `. Run ` PCILeechFlash_Installer.exe `and follow the instructions.
+Clone the PCILeech Github repository. The binaries are found in pcileech_files and should work on 64-bit Windows and Linux. Please copy all files from pcileech_files since some files contains additional modules and signatures.
 
-Flashing in 32-bit Windows or in Windows 7 is not supported.
+#### Windows:
+The Google Android USB driver also have to be installed if USB3380 hardware is used. Download the Google Android USB driver from: http://developer.android.com/sdk/win-usb.html#download Unzip the driver. Open Device Manager. Right click on the computer, choose add legacy hardware. Select install the hardware manually. Click Have Disk. Navigate to the Android Driver, select android_winusb.inf and install.
 
-If flashing fails or if Linux is preferred please see [pcileech_flash/linux](pcileech_flash/linux) for instructions.
+FTDI drivers have to be installed if FPGA is used with FT601 USB3 addon card. FTDI drivers will installed automatically on Windows from Windows Update at first connection. PCILeech also requires 64-bit [`FTD3XX.dll`](http://www.ftdichip.com/Drivers/D3XX/FTD3XXLibrary_v1.2.0.6.zip) which must be downloaded from FTDI and placed alongside `pcileech.exe`.
+
+To mount live ram and target file system as drive in Windows the Dokany file system library must be installed. Please download and install the latest version of Dokany at: https://github.com/dokan-dev/dokany/releases/latest
+
+#### Linux:
+PCILeech on Linux must be run as root. PCILeech also requires libusb. Libusb is probably installed by default - if not install it by running: `apt-get install libusb-1.0-0`.
+
+#### Android:
+Separate instructions for [Android](Android.md).
 
 Examples:
 =========
@@ -158,17 +138,18 @@ Force the usage of a specific device (instead of default auto detecting it). The
 
 Generating Signatures:
 ======================
-PCILeech comes with built in signatures for Windows, Linux, FreeBSD and macOS. For Windows 8.1 or later it is also possible to use the pcileech_gensig.exe program to generate alternative signatures.
+PCILeech comes with built in signatures for Windows, Linux, FreeBSD and macOS. For Windows 10 it is also possible to use the pcileech_gensig.exe program to generate alternative signatures.
 
 Limitations/Known Issues:
 =========================
 * Read and write errors on some hardware with the USB3380. Try `pcileech.exe testmemreadwrite -min 0x1000` to test memory reads and writes against the physical address 0x1000 (or any other address) in order to confirm. If issues exists downgrading to USB2 may help.
+* The PCIeScreamer device may currently experience instability depending on target configuration and any adapters used. 
 * Does not work if the OS uses the IOMMU/VT-d. This is the default on macOS (unless disabled in recovery mode). Windows 10 with Virtualization based security features enabled does not work fully - this is however not the default setting in Windows 10 or Linux.
 * Some Linux kernels does not work. Sometimes a required symbol is not exported in the kernel and PCILeech fails.
 * Linux based on the 4.8 kernel and later might not work with the USB3380 hardware. As an alternative, if target root access exists, compile and insert .ko (pcileech_kmd/linux). If the system is EFI booted an alternative signature exists.
 * Windows 7: signatures are not published.
 * The Linux/Android versions of PCILeech dumps memory slightly slower than the Windows version. Mount target file system and live RAM are also not availabe in the Linux/Android versions.
-* FPGA support for the SP605/FT601 device only exists for Windows. Linux and Android support is planned for the future.
+* FPGA support only exists for Windows. Linux and Android support is planned for the future.
 
 Building:
 =========
@@ -221,6 +202,7 @@ v2.5
 * SP605/FT601: re-designed and improved. NB! FPGA device have to be re-flashed with new bitstream!
 * SP605/TCP: bug fixes.
 
-Latest
+v2.6
+* FPGA: Support for PCIeScreamer and AC701/FT601 devices added.
 * Display command added.
 * Various bug fixes.
diff --git a/usb3380.md b/usb3380.md
new file mode 100644
index 0000000..23b2d12
--- /dev/null
+++ b/usb3380.md
@@ -0,0 +1,29 @@
+USB3380 Hardware:
+=================
+PCILeech uses PCIe hardware devices to read and write from the target system memory. This is achieved by using DMA over PCIe. No drivers are needed on the target system. Check out the [PCILeech](readme.md) project for general information.
+
+PCILeech supports multiple hardware. USB3380 based hardware is only able to read 4GB of memory natively, but is able to read all memory if a kernel module (KMD) is first inserted into the target system kernel. FPGA based hardware is able to read all memory.
+
+<img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_mbp.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_m2.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_shadow.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_dump.gif" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/2df37be67047e19ea2c3f73be67a0ba06fea203d/_gh_mount.jpg" height="150"/><img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/314e527e13e78edd44cc6db2b7c05cfa4a1ce322/_gh_android.jpg" height="150"/>
+
+PCILeech use the PLX Technologies USB3380 chip. The actual chip can be purchased for around $15, but it's more convenient to purchase a development board on which the chip is already mounted. Development boards can be purchased from BPlus Technology, or on eBay / Ali Express. Please note that adapters may be required too depending on your requirements. Please also note that the USB3380 is currently sold out.
+
+http://www.bplus.com.tw/PLX.html
+
+The hardware confirmed working is:
+* USB3380-EVB mini-PCIe card.
+* PP3380-AB PCIe card.
+
+Please note that the ExpressCard EC3380-AB is not working!
+
+Please note that the USB3380-AB EVK-RC kit is not working!
+
+Flashing Hardware:
+==================
+In order to turn the USB3380 development board into a PCILeech device it must be flashed. Flashing may be done in Windows 10 (as administrator) or in Linux (as root). The board must be connected to the system via PCIe when performing the initial flash.
+
+To flash in Windows 10 unzip all contents of the ` flash.zip ` archive found in ` pcileech_files `. Run ` PCILeechFlash_Installer.exe `and follow the instructions.
+
+Flashing in 32-bit Windows or in Windows 7 is not supported.
+
+If flashing fails or if Linux is preferred please see [pcileech_flash/linux](pcileech_flash/linux) for instructions.