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This repository has been archived by the owner on Aug 20, 2024. It is now read-only.

Upgrade to Chisel 3.6 #57

Merged
merged 6 commits into from
Sep 21, 2023
Merged

Upgrade to Chisel 3.6 #57

merged 6 commits into from
Sep 21, 2023

Commits on Sep 21, 2023

  1. port to Chisel 3.6

    @ekiwi
    ekiwi committed Sep 21, 2023
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  2. use circt to generate Verilog

    @ekiwi
    ekiwi committed Sep 21, 2023
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  3. use correct firtool version

    @ekiwi
    ekiwi committed Sep 21, 2023
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  4. Tile.sv

    @ekiwi
    ekiwi committed Sep 21, 2023
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  5. update sbt version

    @ekiwi
    ekiwi committed Sep 21, 2023
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  6. ci: modernize

    @ekiwi
    ekiwi committed Sep 21, 2023
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