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Bug with clock and node emit the same reference #468

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wants to merge 5 commits into from
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Bug with clock and node emit the same reference #468

wants to merge 5 commits into from

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da-steve101
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If a clock is created without a reference val, it is given a name with emit ref which may give it the same name as another node and hence result in invalid verilog

Stephen Tridgell added 5 commits July 27, 2015 18:16
Fix bug where a new clock is given the same name as a node if
d70f0ea 
not created in with a val. Fixed testsuite forcing this behaviour
Merge branch 'chiselUpstream' into clockFix
51006c2 
Conflicts:
	src/main/scala/Verilog.scala
Added a test case for same reset with two clocks, emulator is failing
e7b778b
Moved emitRef logic to Backend, have Verilog call super,
685e686 
fix multiple reset issue by ensuring unique def and correct clock names for unnamed clock
Update tests as ref indexs have now changed
a780336
@da-steve101
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I think perhaps i will rework this.
Emitting multiple declarations is a problem for earlier.
Instead i will put in an assertion and say something like "Internal error: invalid cpp code detected"

@da-steve101
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Closing in favour of cleaner pull request #486 and #487

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