Regarding: Config with private scratchpad, independent data load and shared scratchpad bank as mail box.

[ashuthosh-mr]

Hello everyone!

Currently I am using a rocket configuration with backing scratchpad memory and two big cores. I am simulating using verilator.
Current config:
class MbusScratchpadRocketConfig extends Config(
new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig)

1. I desire to have two big cores with private scratchpad of their own in place of L1 cache and have a shared scratchpad for communication between the cores. Is this configuration possible?
2. If such config is possible, I intend to load instructions and data to each core's memory separately. Currently with the above configuration I am using, I believe instructions is being loaded to the scratchpad (correct me if wrong). Also, that makes 0x8000 0000 address of backing scratchpad overlap with the instruction space right?
3. In other words, I need to include a header file based on core ID. How can I do it? And where are the instructions and data getting loaded by default to.
4. Another configuration I intend to have is each core has private scratchpad and a bank of shared scratchpad to be integrated with constellation. That way, I can scale the design to manycores and have shared scratchpad bank to send and receive messages acting like a mail box in each core. At the same time I can load the instructions and data private to each core separately.

Thank you