What is the reason to uniquify the module names?

[davidmlw]

I saw this python script trying to uniquify the module names. What is the reason behind? I suppose it is not an issue for any EDA flow. And EDA tools can do the job. If there are some reasons, could it be done in firtool?

chipyard/scripts/uniquify-module-names.py

Line 185 in ca9e132

def main():

[harrisonliew]

There was a discussion in #1388 and solved in PRs #1442 and #1452. TL;DR: because Chisel generates both the DUT and testbench, there would be module collisions between synthesized and testbench behavioral versions of the same module without uniquification.

We have an issue open in firtool: llvm/circt#5066.

[davidmlw]

Many thanks. The answer is very clear! @harrisonliew