From 94b62460c596b12c7a3d4188bd3bd252a4cfaffc Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Sun, 17 Sep 2023 08:59:26 +0200
Subject: [PATCH] jtag: shiftDR: (fix daisy chain) when more than one FPGA, a
 sequence of '0' before and/or after must be sent instead of '1' (fix #189 and
 #133

---
 src/jtag.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/jtag.cpp b/src/jtag.cpp
index d368e4e019..53412f6ae7 100644
--- a/src/jtag.cpp
+++ b/src/jtag.cpp
@@ -345,7 +345,7 @@ int Jtag::shiftDR(const uint8_t *tdi, unsigned char *tdo, int drlen, tapState_t
 		if (bits_before > 0) {
 			int n = (bits_before + 7) / 8;
 			uint8_t tx[n];
-			memset(tx, 0xff, n);
+			memset(tx, 0x00, n);
 			read_write(tx, NULL, bits_before, 0);
 		}
 	}
@@ -363,7 +363,7 @@ int Jtag::shiftDR(const uint8_t *tdi, unsigned char *tdo, int drlen, tapState_t
 		if (bits_after > 0) {
 			int n = (bits_after + 7) / 8;
 			uint8_t tx[n];
-			memset(tx, 0xff, n);
+			memset(tx, 0x00, n);
 			read_write(tx, NULL, bits_after, 1);  // its the last force
 												  // tms high with last bit
 		}