From f1b7711c975d58b06f3e416fd27ae04d15d8e21a Mon Sep 17 00:00:00 2001
From: Ed <ed.stott@imperial.ac.uk>
Date: Mon, 19 Feb 2024 10:38:32 +0000
Subject: [PATCH] Add missing Verilog statement termination

---
 src/Renderer/Simulator/Verilog.fs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Renderer/Simulator/Verilog.fs b/src/Renderer/Simulator/Verilog.fs
index fd691da42..f28fcdea1 100644
--- a/src/Renderer/Simulator/Verilog.fs
+++ b/src/Renderer/Simulator/Verilog.fs
@@ -418,7 +418,7 @@ let getVerilogComponent (fs: FastSimulation) (fc: FastComponent) =
     | NotConnected -> ""
 
     | Not -> sprintf "assign %s = ! %s;\n" (outs 0) (ins 0)
-    | GateN (gateType, n) -> sprintf "assign %s = %s" (outs 0) (getVerilogNInputBinaryOp fc.FType ins)
+    | GateN (gateType, n) -> sprintf "assign %s = %s;\n" (outs 0) (getVerilogNInputBinaryOp fc.FType ins)
     | DFFE
     | RegisterE _ -> $"always @(posedge clk) %s{outs 0} <= %s{ins 1} ? %s{ins 0} : %s{outs 0};\n"
     | Counter _ -> $"always @(posedge clk) %s{outs 0} <= %s{ins 2} ? (%s{ins 1} ? %s{ins 0} : (%s{outs 0}+1'b1)) : %s{outs 0};\n"