Design digital circuits in C. Simulate really fast with a regular compiler!
Q: So can it run algorithms without a CPU?
A: Yes, the algorithm gets implemented as hardware, with gates interconnected to match the C code logic. Complex algorithms are possible like rendering graphics as demoed.
Q: Is the simulation that fast?
A: Well, the fastest logic simulator is Verilator, and after some tests converting existing logic cores writen in verilog or migen to CflexHDL (unsing a provided automatic tool), speed gains were 2.5X to 5X, and up to 10X in some cases, compared with the same cores simulated with Verilator (a few tests, but in all cases so far). See DEMOS.md or this video.
See the CflexHDL slides
Install the minimal dependencies including GCC, Python's libclang, Sylefeb's Silice and Verilator. SDL library for graphical simulations. For synthesis on actual hardware, Vivado or Yosys+NextPNR or Quartus, and OpenFPGALoader (currently supports the Arty A7 board and the Terasic DE0-Nano)
$ cd demos/led_glow && make should print simulation results
$ make load synths with default toolchain and loads the bitstream. First time of running the parser needs to be compiled and takes some extra time, just once!
Synth options:
$ make BOARD=de0nano load overrides the default board (the Arty)
$ make XILINXTOOLCHAIN=yosys+nextpnr load overrides the default toolchain for the Arty (Vivado)
$ cd demos/vga && make should bring a window that renders graphics at high FPS (on your PC), and print the FPS on closing.
$ make verilator should bring the same window but at slower FPS
$ make load synths and loads the bitstream on the Arty board with a VGA PMOD on JB-JC. You should be able to see your PC and FPGA both running at 60 FPS*, side to side (the blurring is proof that the image was moving when taking the picture):
See it in action! https://youtu.be/TqV9wUDEG2o
For using yosys+nextpnr toolchain on the Digilent Arty board, use XILINXTOOLCHAIN=yosys+nextpnr in make
For the DE0-Nano board, use $ make BOARD=de0nano bitstream load, the board outputs DVI signals at LVDS levels (use a simple capacitor coupling)
*To limit FPS, set vsync to true when calling fb_init on simulator_main.cpp
See DEMOS page