GDB debugging in simulation!

[NikLeberg]

Hi there!

Just recently I stumbled upon the VHPI (VHDL Procedural Interface) feature of GHDL. It lets you communicate with non-VHDL languages during simulation. Combined with the absurdly simple OpenOCD remote_bitbang I combined this to allow simulation-time debugging with GDB.

The communication channel looks roughtly like so:

+-----+     +---------+     +-------------+     +---------------+     +-----------+
| GDB | <-> | OpenOCD | <-> | vhpi_json.c | <-> | vhpi_json.vhd | <-> | neorv_top |
+-----+  :  +---------+  :  +-------------+  :  +---------------+  :  +-----------+
        TCP         UNIX socket          VHPIDIRECT              JTAG

[        outside GHDL <<] [>> inside GHDL                                         ]

All relevant code is in my repo NikLeberg/vhpi_jtag. In the test subfolder there are all neccessary files (testbench, openocd + configuration) to: compile the VHDL sources, boot up simulation of NEORV32 softcore, start OpenOCD, connect with GDB, upload a precompiled hello_world program, set a breakpoint on main and hit it.

One thing has to be said though.. as you might imagine, all this is not very fast. On my machine (docker on WSL on Windows 11) starting untill hitting the main breakpoint takes about 5 mins. But once we are connected with GDB it is ok.

I see this as a nice method to use in CI environments where runtime is not that relevant. Or with more serious cosimulation workflows.

Let me know if any one of you tried it out. I just find it so fascinating what is possible with a few lines of code.

Thats, all. 😊

[stnolting]

Hey Nik!

Thank you very much for sharing your code - this is really cool! I didn't expect it to be so “simple” (at least the rtl part). I definitely have to try it out for myself.

I always wanted to test the on-chip debugger in the testbench/CI as well. But I didn't want to write all the JTAG stuff by hand... So this would be the perfect solution. 👍

[NikLeberg]

Btw, just testing the dmi interface of the dm is quite simple. You might have seen it already but in neorv32_debug_dm_smp_tb.vhdl I've implemented the hart detection and enumeration sequence that openocd does as testbench.

But I figure that testing the whole chain at once makes more sense.

[stnolting]

You might have seen it already but in neorv32_debug_dm_smp_tb.vhdl I've implemented the hart detection and enumeration sequence that openocd does as testbench.

Oh, that's nice! Thanks for sharing!

I have actually considered implementing such functions. But yes, a complete connection test with GDB + virtual JTAG to print a simple “Hello” on the console would of course be the ultimate testbench! 🚀 😎