Can linux (mmu-less) run on neorv32?

[agamez]

If not, what would it take? If yes, has anyone got a working example?

[stnolting]

Hey @agamez!

In theory this should be possible... Besides an accordingly configured Linux system (device tree etc.) you would need

• some MBs of memory, which could be some DRAM controlled by a dedicated SDRAM controller
• a port of the RISC-V supervisor binary interface (SBI) - at least for handling the MTIME timer and the UART
• CPU supervisor mode "S"

Right now supervisor mode is not implemented. I think it would be possible to emulate everything in machine mode (I have seen that somewhere before), but that would cost a lot of performance.

However, adding supervisor mode basically means adding some more CSRs and actually this is something that is on my To-Do list 😉

[agamez]

I see, it looks like it won't be an easy feat!

I guess supporting burst transactions on the bus would also be, even if not required, pretty much necessary so to get some efficiency of running such a complex code. Since the designs I'm thinking of replacing run microblaze, I would also need a full fledged AXI4 interface to interact with the DDR3 controller from Xilinx.

[stnolting]

I see, it looks like it won't be an easy feat!

Well, yes and no. Adding the supervisor-mode CSRs isn't a big deal. But the entire trap logic would require a makeover as we would have another privilege level (plus all the trap delegation stuff).

I guess supporting burst transactions on the bus would also be, even if not required, pretty much necessary so to get some efficiency of running such a complex code.

Burst accesses are not mandatory, but they would increase processing speed. However, the caches might already help to hide a lot of memory latency.

I would also need a full fledged AXI4 interface to interact with the DDR3 controller from Xilinx.

We already have an AXI-compatible bus wrapper (-> rtl/system_integration/neorv32_SystemTop_axi4lite.vhd). It is "just" AXI-Lite, but maybe that would already be sufficient. But I'm not sure about the atomic memory operations... 🤔