Most appropriate way to stub out unused GPIOs

[jeremyherbert]

Hi,

I'm using the neorv32-verilog repository to try to set up a simple core with 12 GPIOs (actually just outputs are needed). I am a bit of a VHDL newbie though so I am unsure how to proceed. In the documentation, it says set the generic IO_GPIO_NUM to the number of GPIOs needed, and then the remaining bits in the registers will be driven to 0. However, when I try to slice the output bits that are usable, I get an error during synthesis (GHDL): error: no choices for 12 to 63 which is because I am not connecting the upper bits to anything. What is the best way to stub out these bits so that the synthesis tool doesn't complain? I have tried various things like gpio_o(63 downto 12) => (others => open) but it seems you can only open inputs and you cannot associate a vector with open?

Here is my code:

library ieee;
use ieee.std_logic_1164.all;

library neorv32;
use neorv32.neorv32_package.all;

entity neorv32_verilog_wrapper is
  port (
    -- Global control --
    clk_i       : in  std_ulogic; -- global clock, rising edge
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
    -- primary UART0 --
    uart0_txd_o : out std_ulogic; -- UART0 send data
    uart0_rxd_i : in  std_ulogic;  -- UART0 receive data
    gpio_o : out std_logic_vector(11 downto 0)
  );
end entity;

architecture neorv32_verilog_wrapper_rtl of neorv32_verilog_wrapper is

begin

  neorv32_top_inst: neorv32_top
  generic map (
    -- General --
    CLOCK_FREQUENCY            => 100_000_000, -- clock frequency of clk_i in Hz
    INT_BOOTLOADER_EN          => true,        -- boot configuration: boot explicit bootloader
    -- RISC-V CPU Extensions --
    CPU_EXTENSION_RISCV_C      => true,        -- implement compressed extension?
    CPU_EXTENSION_RISCV_M      => true,        -- implement mul/div extension?
    CPU_EXTENSION_RISCV_Zicntr => true,        -- implement base counters?
    -- Internal Instruction memory (IMEM) --
    MEM_INT_IMEM_EN            => true,        -- implement processor-internal instruction memory
    MEM_INT_IMEM_SIZE          => 16*1024,     -- size of processor-internal instruction memory in bytes
    -- Internal Data memory (DMEM) --
    MEM_INT_DMEM_EN            => true,        -- implement processor-internal data memory
    MEM_INT_DMEM_SIZE          => 8*1024,      -- size of processor-internal data memory in bytes
    -- Processor peripherals --
    IO_MTIME_EN                => true,        -- implement machine system timer (MTIME)?
    IO_UART0_EN                => true,        -- implement primary universal asynchronous receiver/transmitter (UART0)?
    IO_UART0_RX_FIFO           => 64,          -- RX fifo depth, has to be a power of two, min 1
    IO_UART0_TX_FIFO           => 64,          -- TX fifo depth, has to be a power of two, min 1

    IO_GPIO_NUM                => 12
  )
  port map (
    -- Global control --
    clk_i       => clk_i,       -- global clock, rising edge
    rstn_i      => rstn_i,      -- global reset, low-active, async
    -- primary UART0 (available if IO_UART0_EN = true) --
    uart0_txd_o => uart0_txd_o, -- UART0 send data
    uart0_rxd_i => uart0_rxd_i,  -- UART0 receive data
    gpio_o(11 downto 0) => gpio_o
  );

end architecture;

Any tips would be greatly appreciated.

[NikLeberg]

Hi @jeremyherbert !
I recommend connecting the gpio_o to an intermediate signal of appropriate size. And then simply just use the lower bits of that signal.

So something like this:

library ieee;
use ieee.std_logic_1164.all;

library neorv32;
use neorv32.neorv32_package.all;

entity neorv32_verilog_wrapper is
  port (
    -- Global control --
    clk_i       : in  std_ulogic; -- global clock, rising edge
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
    -- primary UART0 --
    uart0_txd_o : out std_ulogic; -- UART0 send data
    uart0_rxd_i : in  std_ulogic;  -- UART0 receive data
    gpio_o : out std_logic_vector(11 downto 0)
  );
end entity;

architecture neorv32_verilog_wrapper_rtl of neorv32_verilog_wrapper is
  signal con_gpio : std_ulogic_vector(63 downto 0);
begin

  neorv32_top_inst: neorv32_top
  generic map (
    -- General --
    CLOCK_FREQUENCY            => 100_000_000, -- clock frequency of clk_i in Hz
    INT_BOOTLOADER_EN          => true,        -- boot configuration: boot explicit bootloader
    -- RISC-V CPU Extensions --
    CPU_EXTENSION_RISCV_C      => true,        -- implement compressed extension?
    CPU_EXTENSION_RISCV_M      => true,        -- implement mul/div extension?
    CPU_EXTENSION_RISCV_Zicntr => true,        -- implement base counters?
    -- Internal Instruction memory (IMEM) --
    MEM_INT_IMEM_EN            => true,        -- implement processor-internal instruction memory
    MEM_INT_IMEM_SIZE          => 16*1024,     -- size of processor-internal instruction memory in bytes
    -- Internal Data memory (DMEM) --
    MEM_INT_DMEM_EN            => true,        -- implement processor-internal data memory
    MEM_INT_DMEM_SIZE          => 8*1024,      -- size of processor-internal data memory in bytes
    -- Processor peripherals --
    IO_MTIME_EN                => true,        -- implement machine system timer (MTIME)?
    IO_UART0_EN                => true,        -- implement primary universal asynchronous receiver/transmitter (UART0)?
    IO_UART0_RX_FIFO           => 64,          -- RX fifo depth, has to be a power of two, min 1
    IO_UART0_TX_FIFO           => 64,          -- TX fifo depth, has to be a power of two, min 1

    IO_GPIO_NUM                => 12
  )
  port map (
    -- Global control --
    clk_i       => clk_i,       -- global clock, rising edge
    rstn_i      => rstn_i,      -- global reset, low-active, async
    -- primary UART0 (available if IO_UART0_EN = true) --
    uart0_txd_o => uart0_txd_o, -- UART0 send data
    uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
    gpio_o      => con_gpio
  );

  gpio_o <= con_gpio(11 downto 0);

end architecture;

[jeremyherbert]

Thanks! That looks good and works with GHDL.

[stnolting]

Hey @jeremyherbert!

Most of the time I also use the concept @NikLeberg has shown. But you can also use open for vector slices:

  ...
  gpio_o(11 downto 0)  => gpio_o,
  gpio_o(63 downto 12) => open

[jeremyherbert]

Thanks for your reply. I did try this, but I get this error from GHDL:

error: cannot associate individually with open
    gpio_o(63 downto 12) => open

[stnolting]

Oh, interesting! Lattice Radiant / Synplify has no problem with this... Maybe it is a VHDL2008++ thing? 🤔

[jeremyherbert]

Yeah, I found some forum posts comparing which tools this worked in, but I couldn’t work out if this was just a de facto standard or an offical part of a later standard. If it isn’t, it probably should be!

[stnolting]

So we should better stick to solution @NikLeberg has provided.