NEORV32 is a target for SweetAda

[gabriele-galeotti]

Hi,

don't know if this is the right place, but I would like to inform you that I created
a very little, minimal target example of Ada code running on NEORV32 (simulated
under GHDL), inside the SweetAda repository (https://github.com/gabriele-galeotti/SweetAda).
The code does only initialization and output a message over the simulated UART,
but it works. Maybe one day I will try it even on real hardware.

Hope this is interesting for your project.

G

[stnolting]

That's really cool - thanks for sharing!
So now you can execute Ada applications on the core?

[gabriele-galeotti]

Hi Stephan,

I've finally been able to put the NEORV32 core on a DE10-Lite board, MAX10M50 FPGA.

I've used one of the examples in the repository @ https://github.com/emb4fun/neorv32-examples

Now I have in front of me Ada code running on physical hardware, UART handling + TIMER interrupt
are full working.

Soon I will upload this new target in SweetAda repository @ https://github.com/gabriele-galeotti/SweetAda

[stnolting]

Great news - thanks for sharing!
Do you have any demo setup or tutorial for this? 😉
I would like to test this on my own board as well.

[gabriele-galeotti]

I will pack the project for you, and then upload to my website, just give me a little bit of time.

I generated the SOF HW file out-of-the-box in Quartus from the example project above, with the notice that I/O addresses in that project are different from the current manual hosted here. I don't know if it's only due to an old release, I am pretty new in NEORV32 :)

Indeed there are two setups, one for the GHDL simulator and one for the DE10-Lite, but they run equally well, interrupt timer, UART TX, and some LED pattern blinking also for the DE10-Lite. Clock is set @ 90 MHz, UART brate = 19200.

After JTAG programming with the USB-Blaster, in the project that I am going to pack you will find the binary to be executed with the internal bootloader, but you can build it yourself if you have a GNAT Ada toolchain (and you know how to deal with SweetAda -- sorry, my docs are so far very outdated). In any case, ask everything, I am available for explanations. Current sources are already uploaded in Github in the directory .../platforms/NEORV32.

That being said, I can do more for NEORV32. Nothing sure, but most likely next June I will be an official speaker at the AIEC '24 Ada-Europe International Conference meeting which will take place in Barcelona at the BSC, and I want to expose, besides the whole SweetAda system, this project as part of the demo.

Standby for another post when the packed project will be ready.

[gabriele-galeotti]

Hi Stephan.

I've just uploaded a package for you in my website. Download:

https://www.sweetada.org/packages/SweetAda_for_SN.tar.gz.

There is a MANUAL.txt inside the package, with other support files.
I hope to fullfill your needs.

It's interesting also for me to understand what other people think
about SweetAda. Just ping me if something is not clear, missing or
bad explained, or whatever.

Let me know, bye.

[stnolting]

Thank you so much!
I will have a look at this as the weekend. Hopefully, I will be able to give you some (useful) feedback.

[tmeissner]

I'm also very interested in this project. Had an Ada training last week and now I'm thrilled to do some Ada on the neorv32. Is the code in the sweetAda repository updated to the functionality you wrote 2 weeks ago?

Now I have in front of me Ada code running on physical hardware, UART handling + TIMER interrupt
are full working.

[gabriele-galeotti]

Fine.

Yes, the repository is up-to-date.

I would like to stress about SweetAda being heavily a work in progress, so some language functionalities are limited (no tasks and no protected objects), but basic capabilities are ok.

Feel free to contact me, I will be happy to help you to make SweetAda run on your system.

[tmeissner]

I don't need protected types or tasks, as my FW will be pretty simple. I plan to use a simple main loop which checks for global (volatile) variables set by ISR routines. What has to be working are the interrupts for peripherals like SPI, UART and the Wishbone IF. I will contact you when I'm starting with the project and have questions, thanks 🙂

[gabriele-galeotti]

Just to inform you that NEORV32 has been shown at AEiC '24 just some days ago

https://www.ada-europe.org/conference2024/

A live system of the NEORV32 was running on an ULX3S FPGA, executing SweetAda code.

[stnolting]

Wow great news! 👍 Any chance we can download a paper or video somewhere?

Sorry for the late reply... I accidentally marked this as “done” and then completely forgot about it 🙈

So, I finally looked into the setup you have provided. Thank you very much for all your effort! Unfortunately, I do not have de10-lite board over here (and also no other Intel board at the moment)... Do you also have a setup for a Xilinx board? Maybe a pre-built one for the Arty series? 😅

[gabriele-galeotti]

Hi, no problem. Late reply on my side too, I've got a few days of vacation.

The guys are working for a post-production of the video. It will be ready very soon.

About the Xilinx board, I have a Spartan 3E, but do not know if it is ok for the NEORV32. In any case I'll try to buy something larger board, like the Artix you mention.

It's ok the "Xilinx FPGA Artix7 Artix-7 Development board Artix-7 XC7A100T DDR3 Core board" which I found on ebay ?

In any case, the SweetAda system seems to be ok virtually with every platform, because it's a very software thing, no hardware issues. Currently SweetAda runs on these targets:

1. GHDL simulator
2. DE10-Lite
3. ULX3S FPGA

You could try to send me parameters of your Arty board (addresses, memory map, UART clock, etc) and maybe I'll try to build an executable suitable for the internal bootloader. Else you can try to build SweetAda yourself, but you have to be able to manage the build and you need the Ada compiler (which you can download from AdaCore or build from sources as explained in the "toolchains" directory full of scripts).

Let me know.