error: multiple assignments to array offset

[biosbob]

i'm receiving the following error message when compiling my design:

../em/rtl/neorv32_em_top.vhd:313:12: multiple assignments for "rsp_bus" offsets 849:849
    signal rsp_bus : response_bus_t; -- global response bus

how can i determine what's at offsets 849:849???? my code is based on neorv32_top.vhd, with the type response_bus_t defined in the same way.... at this point, i'm simply trying to determine which member of the device_ids_t set has its corresponding signals within this offset

[stnolting]

Oh, this is a hard one 😅
Here you can find the prototype for one entry in the response bus:

neorv32/rtl/core/neorv32_package.vhd

Lines 334 to 340 in 8ab4ca0

	-- Internal Bus Interface: Response -------------------------------------------------------
	-- -------------------------------------------------------------------------------------------
	type bus_rsp_t is record
	data : std_ulogic_vector(31 downto 0); -- read data
	ack : std_ulogic; -- access acknowledge (single-shot)
	err : std_ulogic; -- access error (single-shot)
	end record;

So one entry (= one device response) has a total width of 32+1+1=34. If you divide 849 by 34 you get 28 point something, so the error might come from the device with index 27.

Do you have Modelsim or Xilinx Vivado available? Or maybe GHDL + GtkWave? Having a graphical waveform might be the easier way of finding the rogue signal assignment.

[biosbob]

that was my original thought, but then realized that a std_ulogic has at least 8-9 different "values" -- which would put offset 849 much earlier in the set....

i did find the problem through visual inspection of my code.... as for looking at a graphical waveform, that requires successfully compiling the .vhd sources -- which is how i got here in the first place 😉

[stnolting]

that was my original thought, but then realized that a std_ulogic has at least 8-9 different "values" -- which would put offset 849 much earlier in the set....

Note: offsets 849:849 does not specify a memory address in you computer's address space. So there is no relation to the number of values a std_logic can contain here. The synthesis tool / simulator just "unwraps" the records in the response bus into a linear array of "wires".

i did find the problem through visual inspection of my code.... as for looking at a graphical waveform, that requires successfully compiling the .vhd sources -- which is how i got here in the first place 😉

👍