Smaller CPU core - How to verify?

[GideonZ]

Hi Stephan!

Last week I wrote my own RiscV core in VHDL. Why? Because I wanted to get rid of a microblaze-variant in an old project, and the NeoRV32 didn't fit in the FPGA. The microblaze compilers are buggy as hell, and since I have had really good results using the Risc-V compiler in combination with NeoRV32, I thought: well, let's give it a shot.

Unlike your amazing NeoRV32, with full documentation and error detection, this core is ultra light. It does not have support for extensions; it only does RV32I + Zicsr for the interrupts, in machine mode only. No counters and other stuff. Including the barrel shifter it is approximately 1300 4-input LUTs in the good old Spartan-3A. However, since it is a 4-stage pipeline, I think performance is quite a bit higher than NeoRV32, well, theoretically, since the I-cache is dumb.

Although I have been able to successfully run the "Hello world" application, I would like to succumb this core to a wider test suite before jumping to the main application, which is dependent on I/O peripherals and what not. If that doesn't work, I'd be blind, so let's take it step by step.

I think you mentioned the RiscV verification suite somewhere in one of the posts, but I don't seem to find it as part of the NeoRV repository. Could you tell me how you have run this verification suite?

Regards,
Gideon

[stnolting]

Hey @GideonZ!

Last week I wrote my own RiscV core in VHDL. Why? Because I wanted to get rid of a microblaze-variant in an old project, and the NeoRV32 didn't fit in the FPGA.

That's awesome! 👍
Do you plan to make it open-source? 😉

I think you mentioned the RiscV verification suite somewhere in one of the posts, but I don't seem to find it as part of the NeoRV repository. Could you tell me how you have run this verification suite?

You can find that in another repository: https://github.com/stnolting/neorv32-riscof

Basically, porting RISCOF is not really complicated. You need a specific linker script, some low-level code to output test signatures and some Python code to do all the housekeeping.

Another nice option to "check" your core would be the porting of CoreMark, which should cover almost all rv32i core instructions.

[GideonZ]

Hey @stnolting!

Thank you so much for your positive reply!

Do you plan to make it open-source? 😉

Well, of course! It is actually already in the public domain, as it is part of a public repository. After cleaning up the files, I will move it to a separate repository and inform you about it.

You can find that in another repository: https://github.com/stnolting/neorv32-riscof Basically, porting RISCOF is not really complicated. [...]

Excellent! I will have a look there.

Another nice option to "check" your core would be the porting of CoreMark, which should cover almost all rv32i core instructions.

Good idea. I will let you know the CoreMark score as soon as I have run it successfully. The main application that I run on NeoRV32 (which includes interrupts and ecall, running FreeRTOS), now also runs on my crippled core, so I think it should not be too difficult to get CoreMark to run as well.